Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)最新文献_第4页

HomeRun 全垒打

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2018-07-23 DOI: 10.1145/3218603.3218633

Chih-Kai Kang, Chun-Han Lin, P. Hsiu, Ming-Syan Chen

引用次数: 2

Designing Efficient Imprecise Adders using Multi-bit Approximate Building Blocks 利用多比特近似构建块设计高效的不精确加法器

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2018-07-23 DOI: 10.1145/3218603.3218638

Sarvenaz Tajasob, Morteza Rezaalipour, M. Dehyadegari, M. N. Bojnordi

{"title":"Designing Efficient Imprecise Adders using Multi-bit Approximate Building Blocks","authors":"Sarvenaz Tajasob, Morteza Rezaalipour, M. Dehyadegari, M. N. Bojnordi","doi":"10.1145/3218603.3218638","DOIUrl":"https://doi.org/10.1145/3218603.3218638","url":null,"abstract":"Energy-efficiency has become a major concern in designing computer systems. One of the most promising solutions to enhance power and energy-efficiency in error tolerant applications is approximate computing that balances accuracy, area, delay, and power consumption based on the computational needs. By trading accuracy of computation, approximate computing may achieve significant improvements in speed, power, and area consumption. Adders are important arithmetic units widely used in almost every digital processing system, which contribute to significant amounts of power dissipation. With the emergence of deep learning tasks and fault tolerant big data processing in every aspect of today's computing, the demand for low-power and energy-efficient approximate adders has increased significantly. Numerous designs have been proposed in the literature that build multi-bit adders using novel approximate full adder circuits. Regrettably, relying on single-bit building blocks only limits the design space of approximate adders and prevents the designers from achieving the most significant benefits of approximate circuits. This paper presents a novel approach to designing imprecise multi-bit adders, based on four novel approximate 2 and 3-bit adder building blocks. The proposed circuits are evaluated and compared with the existing low power adders in terms of various design characteristics, such as area, delay, power, and error tolerance. Our simulation results indicate that the proposed adders achieve more than 60% reduction in power and area consumption compared to the state-of-the-art approximate adders while introducing 12-17% less error in computation.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80403239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

EcoMicro EcoMicro

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2018-07-23 DOI: 10.1145/3218603.3218648

Cheng-Ting Lee, Yun-Hao Liang, Pai H. Chou, A. Gorji, Seyede Mahya Safavi, Wen-Chan Shih, Wen-Tsuen Chen

引用次数: 6

Design Optimization of 3D Multi-Processor System-on-Chip with Integrated Flow Cell Arrays 集成流池阵列的三维多处理器片上系统设计优化

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2018-07-23 DOI: 10.1145/3218603.3218606

A. Andreev, Fulya Kaplan, Marina Zapater, A. Coskun, David Atienza Alonso

引用次数: 5

Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications 用于低vmin物联网和认知应用的6T FinFET sram中的多个组合读写外设辅助

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2018-07-23 DOI: 10.1145/3218603.3218628

A. Banerjee, Sumanth Kamineni, B. Calhoun

{"title":"Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications","authors":"A. Banerjee, Sumanth Kamineni, B. Calhoun","doi":"10.1145/3218603.3218628","DOIUrl":"https://doi.org/10.1145/3218603.3218628","url":null,"abstract":"Battery-operated or energy-harvested IoT and cognitive SoCs in modern FinFET processes prefer the use of low-VMIN SRAMs for ultra-low power (ULP) operations. However, the 1:1:1 high-density (HD) FinFET 6T bitcell faces challenges in achieving a lower VMIN across process variation. The 6T bitcell VMIN improves either by increasing the size of the bitcell or by using combinations of peripheral assists (PAs) since a single PA cannot achieve the best VMIN across process variation. State-of-the-art works show some combinations of write and read PAs that lower the VMIN of 6T FinFET SRAMs. However, the better combinations of PA for 14nm HD 6T FinFET SRAMs are unknown. This work compares all the possible dual combinations of PAs and reveals the better ones. We show that in a usual column mux scenario the combination of negative bitline with VDD boosting and VDD collapse with VDD boosting in a proportion of 14% and 6% (total 20%), respectively, maximize the static VMIN improvement close to 191mV for ULP IoT and cognitive applications. We also show that a combination of wordline boosting with negative bitline and wordline boosting with VSS lowering achieve a 150mV and 25mV of dynamic VMIN improvement at the 5GHz frequency for the worst-case write and read corners, respectively, beating other combinations.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79108014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

RMAC RMAC

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2018-07-23 DOI: 10.1145/3218603.3218621

M. Imani, Ricardo Garcia, Saransh Gupta, Tajana Rosing

{"title":"RMAC","authors":"M. Imani, Ricardo Garcia, Saransh Gupta, Tajana Rosing","doi":"10.1145/3218603.3218621","DOIUrl":"https://doi.org/10.1145/3218603.3218621","url":null,"abstract":"Approximate computing is a way to build fast and energy efficient systems, which provides responses of good enough quality tailored for different purposes. In this paper, we propose a novel approximate floating point multiplier which efficiently multiplies two floating numbers and yields a high precision product. RMAC approximates the costly mantissa multiplication to a simple addition between the mantissa of input operands. To tune the level of accuracy, RMAC looks at the first bit of the input mantissas as well as the first N bits of the result of addition to dynamically estimate the maximum multiplication error rate. Then, RMAC decides to either accept the approximate result or re-execute the exact multiplication. Depending on the value of N, the proposed RMAC can be configured to achieve different levels of accuracy. We integrate the proposed RMAC in AMD southern Island GPU, by replacing RMAC with the existing floating point units. We test the efficiency and accuracy of the enhanced GPU on a wide range of applications including multimedia and machine learning applications. Our evaluations show that a GPU enhanced by the proposed RMAC can achieve 5.2x energydelay product improvement as opposed to GPU using conventional FPUs while ensuring less than 2% quality loss. Comparing our approach with other state-of-the-art approximate multipliers shows that RMAC can achieve 3.1x faster and 1.8x more energy efficient computations while providing the same quality of service.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80028691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

Efficient and Secure Group Key Management in IoT using Multistage Interconnected PUF 使用多级互联PUF的物联网中高效安全的组密钥管理

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2018-07-23 DOI: 10.1145/3218603.3218646

Hongxiang Gu, M. Potkonjak

{"title":"Efficient and Secure Group Key Management in IoT using Multistage Interconnected PUF","authors":"Hongxiang Gu, M. Potkonjak","doi":"10.1145/3218603.3218646","DOIUrl":"https://doi.org/10.1145/3218603.3218646","url":null,"abstract":"Secure group-oriented communication is crucial to a wide range of applications in Internet of Things (IoT). Security problems related to group-oriented communications in IoT-based applications placed in a privacy-sensitive environment have become a major concern along with the development of the technology. Unfortunately, many IoT devices are designed to be portable and light-weight; thus, their functionalities, including security modules, are heavily constrained by the limited energy resources (e.g., battery capacity). To address these problems, we propose a group key management scheme based on a novel physically unclonable function (PUF) design: multistage interconnected PUF (MIPUF) to secure group communications in an energy-constrained environment. Our design is capable of performing key management tasks such as key distribution, key storage and rekeying securely and efficiently. We show that our design is secure against multiple attack methods and our experimental results show that our design saves 47.33% of energy globally comparing to state-of-the-art Elliptic-curve cryptography (ECC)-based key management scheme on average.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74284187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

SPONGE: A Scalable Pivot-based On/Off Gating Engine for Reducing Static Power in NoC Routers 海绵:一个可扩展的基于枢轴的开关门控引擎，用于降低NoC路由器的静态功率

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2018-07-23 DOI: 10.1145/3218603.3218635

Hossein Farrokhbakht, Hadi Mardani Kamali, Natalie D. Enright Jerger, S. Hessabi

{"title":"SPONGE: A Scalable Pivot-based On/Off Gating Engine for Reducing Static Power in NoC Routers","authors":"Hossein Farrokhbakht, Hadi Mardani Kamali, Natalie D. Enright Jerger, S. Hessabi","doi":"10.1145/3218603.3218635","DOIUrl":"https://doi.org/10.1145/3218603.3218635","url":null,"abstract":"Due to high aggregate idle time of Networks-on-Chip (NoCs) routers in practical applications, power-gating techniques have been proposed to combat the ever-increasing ratio of static power. Nevertheless, the sporadic packet arrivals compromise the effectiveness of power-gating by incurring significant latency and energy overhead. In this paper, we propose a Scalable Pivot-based On/Off Gating Engine (SPONGE) which efficiently manages power-gating decisions and routing mechanism by adaptively selecting a small set of powered-on columns of routers and keeping the others in power-gated state. To this end, a router architecture augmented with a novel routing algorithm is proposed in which a packet can traverse powered-off routers without waking them up, and can only turn in predetermined powered-on routers. Experimental results on SPLASH-2 benchmarks demonstrate that, compared to the conventional power-gating method, SPONGE on average not only improves static power consumption by 81.7%, it also improves average packet latency by 63%.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74042981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Road to High-Performance 3D ICs: Performance Optimization Methodologies for Monolithic 3D ICs 高性能3D集成电路之路:单片3D集成电路的性能优化方法

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2018-07-23 DOI: 10.1145/3218603.3218636

Kyungwook Chang, S. Pentapati, D. Shim, S. Lim

引用次数: 5

A Low-power 4096x2160@30fps H.265/HEVC Video Encoder for Smart Video Surveillance 用于智能视频监控的低功耗4096x2160@30fps H.265/HEVC视频编码器

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2018-07-23 DOI: 10.1145/3218603.3218604

Ke Xu, Yu Li, Bo Huang, Xiangkai Liu, Hong Wang, Zhuoyan Wu, Zhanpeng Yan, Xueying Tu, Tongqing Wu, Daibing Zeng

{"title":"A Low-power 4096x2160@30fps H.265/HEVC Video Encoder for Smart Video Surveillance","authors":"Ke Xu, Yu Li, Bo Huang, Xiangkai Liu, Hong Wang, Zhuoyan Wu, Zhanpeng Yan, Xueying Tu, Tongqing Wu, Daibing Zeng","doi":"10.1145/3218603.3218604","DOIUrl":"https://doi.org/10.1145/3218603.3218604","url":null,"abstract":"This paper presents the design and VLSI implementation of a low-power HEVC main profile encoder, which is able to process up to 4096x2160@30fps 4:2:0 encoding in real-time with five-stage pipeline architecture. A pyramid ME (Motion Estimation) engine is employed to reduce search complexity. To compensate for the video sequences with fast moving objects, GME (Global Motion Estimation) are introduced to alleviate the effect of limited search range. We also implement an alternative 5x5 search along with 3x3 to boost video quality. For intra mode decision, original pixels, instead of reconstructed ones are used to reduce pipeline stall. The encoder supports DVFS (Dynamic Voltage and Frequency Scaling) and features three operating modes, which helps to reduce power consumption by 25%. Scalable quality that trades encoding quality for power by reducing size of search range and intra prediction candidates, achieves 11.4% power reduction with 3.5% quality degradation. Furthermore, a lossless frame buffer compression is proposed which reduced DDR bandwidth by 49.1% and power consumption by 13.6%. The entire video surveillance SoC is fabricated with TSMC 28nm technology with 1.96 mm2 area. It consumes 2.88M logic gates and 117KB SRAM. The measured power consumption is 103mW at 350MHz for 4K encoding with high-quality mode. The 0.39nJ/pixel of energy efficiency of this work, which achieves 42% ~ 97% power reduction as compared with reference designs, make it ideal for real-time low-power smart video surveillance applications.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85661034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4