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2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)最新文献

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Figure of merit based design strategy for low-power continuous-time /spl Sigma//spl Delta/ modulators 基于优值图的低功耗连续时间/spl Sigma//spl Delta调制器设计策略
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) Pub Date : 2002-08-07 DOI: 10.1109/ISCAS.2002.1010432
F. Gerfers, Kian Min Soh, M. Ortmanns, Y. Manoli
{"title":"Figure of merit based design strategy for low-power continuous-time /spl Sigma//spl Delta/ modulators","authors":"F. Gerfers, Kian Min Soh, M. Ortmanns, Y. Manoli","doi":"10.1109/ISCAS.2002.1010432","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010432","url":null,"abstract":"This paper presents a novel design strategy for low-power continuous-time (CT) /spl Sigma//spl Delta/ modulators. The figure of merit (FOM) is used to find the optimal /spl Sigma//spl Delta/ modulator implementation with respect to a minimal power consumption on the one hand and to fulfil a rapid prototyping approach on the other hand. This method compares the power efficiency of different modulator structures and modulator orders with respect to the given design specifications. The efficiency of this strategy is shown by measurement results of a 1.5V 3/sup rd/ order CT modulator.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132762151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs 集成电路设计知识产权保护的物理设计水印方案的层次结构
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) Pub Date : 2002-08-07 DOI: 10.1109/ISCAS.2002.1010594
R. Newbould, J. Carothers, Jeffrey J. Rodríguez, W. T. Holman
{"title":"A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs","authors":"R. Newbould, J. Carothers, Jeffrey J. Rodríguez, W. T. Holman","doi":"10.1109/ISCAS.2002.1010594","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010594","url":null,"abstract":"A method is presented for embedding the same watermark multiple times into a single integrated circuit design using a hierarchy of incorporation techniques. This has the advantage of adding multiple independent signatures to the circuit in order to better resist large-scale attacks. A high degree of robustness is provided by requiring attacks on multiple stages of the VLSI design flow in order to properly efface the mark.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133257501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Magnetizing inrush current of a transformer and a new technique of its computation 变压器励磁涌流及其计算新技术
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) Pub Date : 2002-08-07 DOI: 10.1109/ISCAS.2002.1010249
M. Ogawa
{"title":"Magnetizing inrush current of a transformer and a new technique of its computation","authors":"M. Ogawa","doi":"10.1109/ISCAS.2002.1010249","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010249","url":null,"abstract":"A new computing technique of magnetic nonlinear transients is presented. As an alternative to conventional methods, the technique represents the magnetic nonlinearity by multiple characteristics of coil current versus differential inductance. Magnetizing inrush currents of a transformer are computed by the technique. Comparison with experimented results confirmed effectiveness of this computing technique.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131329746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new method to increase the dynamic range of switched op amp delta-sigma modulators 一种提高开关运放δ - σ调制器动态范围的新方法
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) Pub Date : 2002-08-07 DOI: 10.1109/ISCAS.2002.1011429
A. Varzaghani, M. Atarodi
{"title":"A new method to increase the dynamic range of switched op amp delta-sigma modulators","authors":"A. Varzaghani, M. Atarodi","doi":"10.1109/ISCAS.2002.1011429","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1011429","url":null,"abstract":"Switched op amp technique has shown its capability to operate with very low supply voltages without a demand for voltage multiplication. But it has not achieved the performance of the switched capacitor circuits yet. In this paper one of the nonideal factors, which degrades the performance of the switched Op amp circuits, has been introduced and a solution has been proposed for it. A second order delta-sigma modulator has been designed with this method and has achieved an excellent DR of 90 dB and a very low power consumption of 200 /spl mu/W while operating with a 1.8-volt supply.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"694 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127224782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Current-mode leapfrog ladder filters using CDBAs 使用cdba的电流模式跨越式阶梯滤波器
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) Pub Date : 2002-08-07 DOI: 10.1109/ISCAS.2002.1010639
W. Tangsrirat, N. Fujii, W. Surakampontorn
{"title":"Current-mode leapfrog ladder filters using CDBAs","authors":"W. Tangsrirat, N. Fujii, W. Surakampontorn","doi":"10.1109/ISCAS.2002.1010639","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010639","url":null,"abstract":"In this paper, a possible realization of a current differencing buffered amplifier (CDBA) in the low-voltage operation is proposed. A leapfrog simulation of the current-mode ladder network using the CDBAs as active circuit building blocks is then introduced. In order to demonstrate that the CDBA considerably simplifies the leapfrog structure of the current-mode ladder filters, a fifth-order Butterworth low-pass filter and a sixth-order Chebyshev bandpass filter which require a minimum of active components will be presented. PSPICE simulation results are employed to verify the correctness of the realization procedure.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133815338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Design, double sided post-processing, and packaging of CMOS compatible bio-MEMS device arrays CMOS相容生物mems元件阵列之设计、双面后处理与封装
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) Pub Date : 2002-08-07 DOI: 10.1109/ISCAS.2002.1009928
J. Christen, Cristina E. Davis, Min Li, A. Andreou
{"title":"Design, double sided post-processing, and packaging of CMOS compatible bio-MEMS device arrays","authors":"J. Christen, Cristina E. Davis, Min Li, A. Andreou","doi":"10.1109/ISCAS.2002.1009928","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1009928","url":null,"abstract":"Methods for design, double-sided post-processing and packaging of commercially fabricated CMOS chips for Bio-MEMS applications are presented. These techniques apply to a wide range of devices and allow for both electrical and optical stimulation and assessment of biological specimens. The techniques are straightforward and can be applied to dies fabricated through state of the art CMOS foundries. The resulting assemblies are designed to withstand environments commonly necessary for working with the biological materials such as biological temperatures, pressures, and moisture or autoclave. The proposed packaging is extremely versatile and can be modified to accommodate numerous additions to the system such as syringe inlets or mountable elements.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"149 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115444716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Towards fast solid state DNA sequencing 迈向快速固态DNA测序
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) Pub Date : 2002-08-07 DOI: 10.1109/ISCAS.2002.1010416
S. Iyer, C. Toumazou, J. Georgiou
{"title":"Towards fast solid state DNA sequencing","authors":"S. Iyer, C. Toumazou, J. Georgiou","doi":"10.1109/ISCAS.2002.1010416","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010416","url":null,"abstract":"The current most widely used method for DNA sequencing is the chain termination method or Sanger technique. Many attempts are being made to improve upon this method particularly with regard to the elimination of the latter stage of electrophoresis. Using the ion sensitive field effect transistor and low power signal processing techniques, the possibility of intelligent solid state DNA sequencing is explored.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115591518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Class-N high-frequency power amplifier n类高频功率放大器
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) Pub Date : 2002-08-07 DOI: 10.1109/ISCAS.2002.1010754
A. Rudiakova, M. Kazimierczuk, J. V. Rassokhin, V. Krizhanovski
{"title":"Class-N high-frequency power amplifier","authors":"A. Rudiakova, M. Kazimierczuk, J. V. Rassokhin, V. Krizhanovski","doi":"10.1109/ISCAS.2002.1010754","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010754","url":null,"abstract":"A new class of high-efficiency amplification is introduced. It based on the reduction of time-average dissipation in transistor power instead of state-of-the-art reduction of instantaneous dissipated power. This becomes possible due the influence of capacitance currents that produce a negative collector current swing during a part of AC-period. In this case, along with an always-positive collector-emitter voltage, the instant dissipated power also is negative. A high-efficiency BJT power amplifier was simulated in order to demonstrate the new class features.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115714641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pseudo dynamic logic (SDL): a high-speed and low-power dynamic logic family 伪动态逻辑(SDL):一种高速、低功耗的动态逻辑族
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) Pub Date : 2002-08-07 DOI: 10.1109/ISCAS.2002.1010206
G. Chaji, S. M. Fakhraie, Kenneth C. Smith
{"title":"Pseudo dynamic logic (SDL): a high-speed and low-power dynamic logic family","authors":"G. Chaji, S. M. Fakhraie, Kenneth C. Smith","doi":"10.1109/ISCAS.2002.1010206","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010206","url":null,"abstract":"In this paper, a new logic-design style called Pseudo Dynamic Logic (SDL) is introduced. In this logic-design style, the internal nodes of the logic circuits are not precharged to high or low values, rather the initial charges on nodes are shared to yield an intermediate precharge value for faster evaluation. A 32-bit adder has been designed and simulated using HSPICE Level-49 parameters of a 0.6 /spl mu/m CMOS process. Simulated measurements on this adder show that the worst-case delay is 1.56 ns. This demonstrates 2.1 times speed improvement in comparison to a domino dynamic logic design implemented with the same technology.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124326663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A novel semi-private watermarking technique 一种新型的半私有水印技术
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) Pub Date : 2002-08-07 DOI: 10.1109/ISCAS.2002.1010301
P. Wong, Oscar C. Au
{"title":"A novel semi-private watermarking technique","authors":"P. Wong, Oscar C. Au","doi":"10.1109/ISCAS.2002.1010301","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010301","url":null,"abstract":"A novel watermarking technique is proposed to embed a semi-watermark in digital images. Before embedding the watermark, a M-dimensional vector is extracted from the original data. Watermarking is achieved by modifying this vector to another particular vector according to the private keys and the watermark. A dual-key system is used to reduce the chance for the removal of watermark. The watermark can be detected without the original image. If the original image is available in the detection of watermark, the proposed technique is almost equivalent to the well known spread spectrum technique.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114814537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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