集成电路设计知识产权保护的物理设计水印方案的层次结构

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) Pub Date : 2002-08-07 DOI:10.1109/ISCAS.2002.1010594

R. Newbould, J. Carothers, Jeffrey J. Rodríguez, W. T. Holman

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引用次数: 12

摘要

提出了一种利用分层嵌入技术在单个集成电路中多次嵌入同一水印的方法。这样做的好处是可以在电路中加入多个独立签名，从而更好地抵御大规模攻击。为了正确地消除标记，需要对VLSI设计流程的多个阶段进行攻击，从而提供了高度的鲁棒性。

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A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs

A method is presented for embedding the same watermark multiple times into a single integrated circuit design using a hierarchy of incorporation techniques. This has the advantage of adding multiple independent signatures to the circuit in order to better resist large-scale attacks. A high degree of robustness is provided by requiring attacks on multiple stages of the VLSI design flow in order to properly efface the mark.

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来源期刊

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

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