M. Koledintseva, Amendra Koul, Fan Zhou, J. Drewniak, S. Hinaga
{"title":"Surface impedance approach to calculate loss in rough conductor coated with dielectric layer","authors":"M. Koledintseva, Amendra Koul, Fan Zhou, J. Drewniak, S. Hinaga","doi":"10.1109/ISEMC.2010.5711380","DOIUrl":"https://doi.org/10.1109/ISEMC.2010.5711380","url":null,"abstract":"The analysis presented herein contains closed-form analytical expressions to calculate attenuation in a layered structure “rough metal-dielectric-dielectric”, which is a practically important problem in separating dielectric loss from rough conductor loss in actual PCB stripline geometries, when measuring dielectric constant (Dk) and dissipation factor (Df) using travelling wave S-parameter methods. This approach is based on the surface impedance concept. It is shown that the presence of an epoxy layer on the conductor may affect extracted dielectric parameters, of a PCB substrate, especially the Df data.","PeriodicalId":201448,"journal":{"name":"2010 IEEE International Symposium on Electromagnetic Compatibility","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121706756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fan Zhou, Songping Wu, D. Pommerenke, Y. Kayano, H. Inoue, K. Tan, J. Fan
{"title":"Improvements in GMI probe design for time-domain transient current measurements","authors":"Fan Zhou, Songping Wu, D. Pommerenke, Y. Kayano, H. Inoue, K. Tan, J. Fan","doi":"10.1109/ISEMC.2010.5711297","DOIUrl":"https://doi.org/10.1109/ISEMC.2010.5711297","url":null,"abstract":"Measurement techniques for time-domain transient currents are widely needed in many EMC applications. Demonstrated to have a lot of potential for this purpose, giant magnetio-impedance (GMI) probes are studied in this paper. Improvements in the probe design, including a balanced circuit for increased signal to noise ratio and an on-probe magnetic-field bias circuit, are proposed. These improvements in the probe design make the GMI probes more suitable for practical applications of time-domain transient current measurements.","PeriodicalId":201448,"journal":{"name":"2010 IEEE International Symposium on Electromagnetic Compatibility","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126802571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Full-wave evaluation of carbon nanotubes as microwave interconnects","authors":"Kichul Kim, P. Rice, P. Kabos, D. Filipović","doi":"10.1109/ISEMC.2010.5711391","DOIUrl":"https://doi.org/10.1109/ISEMC.2010.5711391","url":null,"abstract":"Microwave interconnect configurations composed of single wall carbon nanotubes (CNTs) are studied in this paper. Specifically, an atomic layer deposition (ALD) enabled nano-coaxial line with individual CNTs comprising the inner conductor, CNT Goubau line with ALD enabled alumina coating, a nano-coaxial line with inner conductor composed of CNT bundles, and Goubau lines of CNT bundles are discussed. The characteristic impedance and losses of these interconnects are compared with the similar size copper-based transmission lines. Full wave simulations with incorporated quantum effects are conducted using finite element and method of moments tools ANSYS HFSS 1 and EMSS FEKO1, respectively. A thorough modeling validation, interconnect design and analysis are carried out over the wide microwave spectrum. Obtained results clearly show that although their inherent loss and impedance are high, the CNT interconnects can indeed outperform their copper counterparts with lower loss and impedance, and that observation is reinforced with decreasing the CNT radius.","PeriodicalId":201448,"journal":{"name":"2010 IEEE International Symposium on Electromagnetic Compatibility","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126143776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Examining the true effectiveness of loading a reverberation chamber: How to get your chamber consistently loaded","authors":"J. Coder, J. Ladbury, C. Holloway, K. Remley","doi":"10.1109/ISEMC.2010.5711332","DOIUrl":"https://doi.org/10.1109/ISEMC.2010.5711332","url":null,"abstract":"In this paper we explore how placing the same amount of absorber in different locations within a reverberation chamber can have different loading effects. This difference can have a significant impact on measurement reproducibility, both for measurements in the same chamber and measurements between chambers (i.e., round robin style testing). We begin by discussing some of the theories behind this and show some experimental results from different absorber placements in a reverberation chamber. We conclude with some suggestions to ensure absorber is placed consistently.","PeriodicalId":201448,"journal":{"name":"2010 IEEE International Symposium on Electromagnetic Compatibility","volume":"342 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126029179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Development of equivalent circuit model with transmission line model for designing filters formed on printed circuit boards","authors":"Keisuke Matsumoto, Y. Toyota, K. Iokibe, R. Koga","doi":"10.1109/ISEMC.2010.5711287","DOIUrl":"https://doi.org/10.1109/ISEMC.2010.5711287","url":null,"abstract":"The slit pattern formed on the return plane of printed circuit boards (PCBs) acts like a passive element and a defected ground structure (DGS) is one of them. In this paper, we propose an equivalent circuit model with a transmission line model for use in DGS with a filter characteristics. The characteristics of DGS are easily varied with the slit pattern. Thus, DGS is expected to be used for various applications such as a common-mode filter in differential signaling systems. Since a design method has yet to be developed, however, we need to establish a design method for the slit pattern. Some equivalent circuit models have been used, but the models that consist of lumped elements require a full-wave simulation. In addition, the values of the lumped elements do not relate to the physical parameters. Therefore it is not useful for designing filters. In contrast, the equivalent circuit model we propose in this paper will have a great contribution to designing filters with optimum performances and fit for size reduction on PCBs because the transmission line model relates to the physical parameters. As a result, by comparing the transmission characteristics calculated with both a full-wave simulator and a circuit simulator with the proposed equivalent circuit model, the first stop-band width calculated by using the circuit simulator was in agreement with the full-wave simulator.","PeriodicalId":201448,"journal":{"name":"2010 IEEE International Symposium on Electromagnetic Compatibility","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125897425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Switching voltage regulator noise coupling to signal lines in a server system","authors":"G. Ouyang, X. Ye, Trung-Thu Nguyen","doi":"10.1109/ISEMC.2010.5711250","DOIUrl":"https://doi.org/10.1109/ISEMC.2010.5711250","url":null,"abstract":"This paper studies a real-world signal Integrity problem due to switching voltage-regulator (VR) noise coupling in a multi-processor server system. The fast switching of the VR FETs causes significant performance degradation on signal lines in proximity. The major source of the degradation is the high di/dt noise induced by FETs switching. The coupling mechanism is mutual inductive coupling between the VR transient current loop and the loop of differential signal pair. Solutions were identified by decreasing di/dt of the aggressor and optimizing component layout to reduce mutual inductance. General VR design methodology improvements are also discussed to address signal integrity concerns.","PeriodicalId":201448,"journal":{"name":"2010 IEEE International Symposium on Electromagnetic Compatibility","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126707312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis of return path discontinuities in multilayer PCBs and their impact on the signal and power integrity","authors":"A. Ciccomancini Scogna, E. Bogatin","doi":"10.1109/ISEMC.2010.5711237","DOIUrl":"https://doi.org/10.1109/ISEMC.2010.5711237","url":null,"abstract":"This paper investigates the impact of return path discontinuities on both signal and power integrity of high speed interconnects. A test board is built for the purpose and 4 different configurations are analyzed and correlation between measurements and simulations (coming from a full wave 3D EM field simulator) results is also presented. Both time and frequency domain results are analyzed and design guidelines are provided. It is observed that return path discontinuities have a sensible impact on ground bounce in single-ended signals; however the differential signaling can drastically reduces it. Discontinuities from gaps in return paths (e.g. plane splits) and connectors impact the differential signals on both insertion loss and cross talk. The real value of return/grounding vias is to reduce the common signal noise.","PeriodicalId":201448,"journal":{"name":"2010 IEEE International Symposium on Electromagnetic Compatibility","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127176213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Effects of a wire beneath the ground plane on antenna coupling through a slot","authors":"T. Morioka, K. Hirasawa","doi":"10.1109/ISEMC.2010.5711315","DOIUrl":"https://doi.org/10.1109/ISEMC.2010.5711315","url":null,"abstract":"Antenna characteristics, such as input impedance are considerably deviated from those in free space when another antenna is located in the vicinity of the antenna. This often causes system degradation problems. In the present paper, effects of a parasitic wire located beneath the slotted ground plane are investigated on the coupling between monopole antennas above the ground plane. The method of moments is applied to the problem and a combined matrix formulation that includes mutual coupling effects between the elements located in both regions is newly introduced. It is shown that a wire beneath the ground plane considerably affects coupling characteristics between two monopoles above the ground plane when the slot resonates.","PeriodicalId":201448,"journal":{"name":"2010 IEEE International Symposium on Electromagnetic Compatibility","volume":"129 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113987853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jianmin Zhang, Q. Chen, J. Fan, J. Drewniak, Antonio Orland, B. Archambeault
{"title":"DC blocking via structure optimization and measurement correlation for SerDes channels","authors":"Jianmin Zhang, Q. Chen, J. Fan, J. Drewniak, Antonio Orland, B. Archambeault","doi":"10.1109/ISEMC.2010.5711337","DOIUrl":"https://doi.org/10.1109/ISEMC.2010.5711337","url":null,"abstract":"SerDes (Serializer/DeSerializer) is widely used in gigabit Ethernet systems, fiber-optic communication systems, and storage applications for high-speed data transmission between different ASICs (application-specific integrated circuit) with the significant advantage of saving package pin numbers. The channel connecting the Serializer/DeSerializer in two different ASICs on a PCB (Printed Circuit Board) is the SerDes channel defined in the paper. Since DC biases in different ASICs are usually different for their Serializer/DeSerializer circuits, DC blocking capacitors are then necessary to block the DC path for signal transmission through the SerDes channel. It is known that the trace impedance on a PCB can be well controlled in manufacturing while it is difficult for a DC blocking via structure. Therefore, the blocking via structure is the main discontinuity contributor of the SerDes channel. In this paper, two different DC blocking via structures are studied. The performances of the two structures are compared and correlated up to 20 GHz with full-wave modelling and measurements. This study reveals the advantages/disadvantages of the two via blocking structures. A via optimization tool, which is based on the cavity resonance algorithm to speed up the optimization, is used to obtain the optimized parameters for the two blocking via structures, and the following full-wave simulations give further performance explorations of the two via structures.","PeriodicalId":201448,"journal":{"name":"2010 IEEE International Symposium on Electromagnetic Compatibility","volume":"34 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114097331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reduction of heatsink emissions by application of lossy materials","authors":"E. Chikando, S. Connor, B. Archambeault","doi":"10.1109/ISEMC.2010.5711278","DOIUrl":"https://doi.org/10.1109/ISEMC.2010.5711278","url":null,"abstract":"This paper investigates the benefits of high permittivity and permeability RF materials on electromagnetic interference (EMI) performance of integrated circuit (IC) heatsinks. An analysis of lossy materials using Finite-Difference Time-Domain (FDTD) simulations is presented and findings are supported by experimental measurements carried out in both reverberation chamber (RC) and Semi-Anechoic Chamber (SAC) environments.","PeriodicalId":201448,"journal":{"name":"2010 IEEE International Symposium on Electromagnetic Compatibility","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123968891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}