{"title":"Switching voltage regulator noise coupling to signal lines in a server system","authors":"G. Ouyang, X. Ye, Trung-Thu Nguyen","doi":"10.1109/ISEMC.2010.5711250","DOIUrl":null,"url":null,"abstract":"This paper studies a real-world signal Integrity problem due to switching voltage-regulator (VR) noise coupling in a multi-processor server system. The fast switching of the VR FETs causes significant performance degradation on signal lines in proximity. The major source of the degradation is the high di/dt noise induced by FETs switching. The coupling mechanism is mutual inductive coupling between the VR transient current loop and the loop of differential signal pair. Solutions were identified by decreasing di/dt of the aggressor and optimizing component layout to reduce mutual inductance. General VR design methodology improvements are also discussed to address signal integrity concerns.","PeriodicalId":201448,"journal":{"name":"2010 IEEE International Symposium on Electromagnetic Compatibility","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Symposium on Electromagnetic Compatibility","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISEMC.2010.5711250","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 26
Abstract
This paper studies a real-world signal Integrity problem due to switching voltage-regulator (VR) noise coupling in a multi-processor server system. The fast switching of the VR FETs causes significant performance degradation on signal lines in proximity. The major source of the degradation is the high di/dt noise induced by FETs switching. The coupling mechanism is mutual inductive coupling between the VR transient current loop and the loop of differential signal pair. Solutions were identified by decreasing di/dt of the aggressor and optimizing component layout to reduce mutual inductance. General VR design methodology improvements are also discussed to address signal integrity concerns.