{"title":"Dual-LFSR Reseeding for Low Power Testing","authors":"Lung-Jen Lee, W. Tseng, Wenjie. Yang","doi":"10.1109/MTV.2012.15","DOIUrl":"https://doi.org/10.1109/MTV.2012.15","url":null,"abstract":"Large test data volume and excessive test power are two strict challenges for VLSI testing. This paper presents a BIST scheme adopting dual-LFSR reseeding method to effectively reduce the amount of test data while keeping the scan-in power as low. Experimental results show that, compared with the similar work, test data volume can be significantly reduced with a roughly equal scan-in power reduction.","PeriodicalId":201401,"journal":{"name":"2012 13th International Workshop on Microprocessor Test and Verification (MTV)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133582709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Biruk Mammo, J. Larimer, M. Morgan, Da-juan Fan, Eric Hennenhoefer, V. Bertacco
{"title":"Architectural Trace-Based Functional Coverage for Multiprocessor Verification","authors":"Biruk Mammo, J. Larimer, M. Morgan, Da-juan Fan, Eric Hennenhoefer, V. Bertacco","doi":"10.1109/MTV.2012.12","DOIUrl":"https://doi.org/10.1109/MTV.2012.12","url":null,"abstract":"Functional coverage plays a pivotal role in assuring the quality of input stimuli used in the verification of modern digital designs. For an out-of-order multi-processor design, simulation of a detailed model of the design is often required to observe relevant design behaviors for functional coverage. However, since such a model is not available during the early phases of test development, verification teams are forced to wait until much later in the verification process to evaluate the quality of their test cases. Even then, the quality of the tests can be assured only on one specific design implementation - an undesirable characteristic for test and regression suites that are meant to be used across multiple generations and/or implementations of an architecture. This work addresses this issue by presenting a novel, implementation-independent, execution trace-based, coverage collection solution. Our solution enables the early evaluation of multi-processor tests using a high-level model of a design. In addition, it can be deployed with detailed design models, if desired, for further analysis alongside implementation-specific coverage models.","PeriodicalId":201401,"journal":{"name":"2012 13th International Workshop on Microprocessor Test and Verification (MTV)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121024237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automatic Formal Correspondence Checking of ISA and RTL Microprocessor Description","authors":"Lukás Charvát, A. Smrčka, Tomáš Vojnar","doi":"10.1109/MTV.2012.19","DOIUrl":"https://doi.org/10.1109/MTV.2012.19","url":null,"abstract":"The paper proposes an automated approach with a formal basis designed for checking correspondence between an RTL implementation of a microprocessor and a description of its instruction set architecture (ISA). The goals of the approach are to find bugs not discovered by functional verification, to minimize user intervention in the verification process, and to provide a developer with practical results within a short period of time. The main idea is to use bounded model checking to check that the output produced by automatically derived RTL and ISA models of a given processor are the same for each instruction and each possible input. Although the approach does not provide full formal verification, experiments with the approach confirm that due to a different way it explores the state space of the design under test, it can find bugs not found by functional verification, and is thus a useful complement to functional verification.","PeriodicalId":201401,"journal":{"name":"2012 13th International Workshop on Microprocessor Test and Verification (MTV)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131167860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lyl M. Ciganda Brasca, M. Gaudesi, E. Lutton, E. Sánchez, Giovanni Squillero, A. Tonda
{"title":"Automatic Generation of On-Line Test Programs through a Cooperation Scheme","authors":"Lyl M. Ciganda Brasca, M. Gaudesi, E. Lutton, E. Sánchez, Giovanni Squillero, A. Tonda","doi":"10.1109/MTV.2012.17","DOIUrl":"https://doi.org/10.1109/MTV.2012.17","url":null,"abstract":"Test programs for Software-based Self-Test (SBST) can be exploited during the mission phase of microprocessor-based systems to periodically assess hardware integrity. However, several additional constraints must be imposed due to the coexistence of test programs with the mission application. This paper proposes a method for the generation of SBST on-line test programs for embedded RISC processors, systems where the impact of on-line constraints is significant. The proposed strategy exploits an evolutionary optimizer that is able to create a complete test set of programs relying on a new cooperative scheme. Experimental results showed high fault coverage values on two different modules of a MIPS-like processor core. These two case studies demonstrate the effectiveness of the technique and the low human effort required for its implementation.","PeriodicalId":201401,"journal":{"name":"2012 13th International Workshop on Microprocessor Test and Verification (MTV)","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115021788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}