2012 13th International Workshop on Microprocessor Test and Verification (MTV)最新文献

Localization of Bugs in Processor Designs Using zamiaCAD Framework 利用zamiaCAD框架定位处理器设计中的bug

2012 13th International Workshop on Microprocessor Test and Verification (MTV) Pub Date : 2012-12-10 DOI: 10.1109/MTV.2012.20

A. Tsepurov, Valentin Tihhomirov, M. Jenihhin, J. Raik, Gunter Bartsch, Jorge Hernán Meza Escobar, H. Wuttke

引用次数: 7

New Process to Simultaneously Measure, Quantify, and Model Energy Efficient Performance 同时测量、量化和模拟节能性能的新过程

2012 13th International Workshop on Microprocessor Test and Verification (MTV) Pub Date : 2012-12-10 DOI: 10.1109/MTV.2012.13

M. Mattwandel

{"title":"New Process to Simultaneously Measure, Quantify, and Model Energy Efficient Performance","authors":"M. Mattwandel","doi":"10.1109/MTV.2012.13","DOIUrl":"https://doi.org/10.1109/MTV.2012.13","url":null,"abstract":"The term Energy Efficient Performance has been used for over a decade to describe high performance at optimized power levels. While power characterization methods and formal performance assessment techniques are well established and utilized, no standard exists to quantify both metrics simultaneously as a means to establish energy efficient performance. As energy budgets continue to shrink and the expectation for increased performance remains, the need for a process that simultaneously models power versus performance tradeoffs becomes ever more critical. This paper describes a new process developed, prototyped, and implemented in Intel's client post-Si validation labs that is actively being used to measure, process, and model energy efficient performance. The paper will describe methods that simultaneously acquire power and performance measurements, post-process that power data into energy measurements, and model multi-dimensional energy vs. performance tradeoffs. It will also demonstrate how the process is actively being applied to isolate negative energy efficient performance outliers for debug and to tune for best energy efficient performance across multiple product segments.","PeriodicalId":201401,"journal":{"name":"2012 13th International Workshop on Microprocessor Test and Verification (MTV)","volume":"245 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114218012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Case Study: Verification Framework of Samsung Reconfigurable Processor 案例研究:三星可重构处理器验证框架

2012 13th International Workshop on Microprocessor Test and Verification (MTV) Pub Date : 2012-12-10 DOI: 10.1109/MTV.2012.11

Youngchul Cho, Seonghun Jeong, J. Jeong, H. Shim, Yenjo Han, Soojung Ryu, Jay Kim

{"title":"Case Study: Verification Framework of Samsung Reconfigurable Processor","authors":"Youngchul Cho, Seonghun Jeong, J. Jeong, H. Shim, Yenjo Han, Soojung Ryu, Jay Kim","doi":"10.1109/MTV.2012.11","DOIUrl":"https://doi.org/10.1109/MTV.2012.11","url":null,"abstract":"The SRP (Samsung Reconfigurable Processor) is a high-performance, low-power digital signal processor that supports two different operating modes: the VLIW (very long instruction word) mode for running control-intensive code and the CGA (coarse-grained reconfigurable array) mode for running computation-intensive code. In the SRP, an application starts in the VLIW mode, and then may switch back and forth many times between the CGA mode and the VLIW mode throughout its lifetime. In order to support this switching back and forth seamlessly, our C compiler for SRP is capable of generating an executable binary that contain codes for both VLIW and CGA modes. The unusual complexity of SRP verification originates from the unconventional processor architecture/micro-architecture and the complexity of our compiler. In order to manage the unconventional burden that confronts SRP verification engineers, we have aimed to build a scalable verification framework that is both flexible and efficient. In this paper, we report our experience so far, including our effort to be systematic and thorough in our approach.","PeriodicalId":201401,"journal":{"name":"2012 13th International Workshop on Microprocessor Test and Verification (MTV)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125613246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Guaranteeing Termination of Fully Symbolic Timed Forward Model Checking 保证全符号定时前向模型检验终止

2012 13th International Workshop on Microprocessor Test and Verification (MTV) Pub Date : 2012-12-10 DOI: 10.1109/MTV.2012.22

Georges Morbé, Christoph Scholl

引用次数: 0

Deterministic ATPG for Low Capture Power Testing 低捕获功率测试的确定性ATPG

2012 13th International Workshop on Microprocessor Test and Verification (MTV) Pub Date : 2012-12-10 DOI: 10.1109/MTV.2012.14

Lung-Jen Lee, Chia-Cheng He, W. Tseng

引用次数: 6

Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis 通过RTL-to-TLM抽象和TLM综合重新设计和验证RTL ip

2012 13th International Workshop on Microprocessor Test and Verification (MTV) Pub Date : 2012-12-10 DOI: 10.1109/MTV.2012.21

N. Bombieri, F. Fummi, V. Guarnieri, G. Pravadelli, S. Vinco

引用次数: 4

On the Reuse of RTL IPs for SysML Model Generation RTL ip在SysML模型生成中的重用

2012 13th International Workshop on Microprocessor Test and Verification (MTV) Pub Date : 2012-12-10 DOI: 10.1109/MTV.2012.10

N. Bombieri, E. Ebeid, F. Fummi, M. Lora

引用次数: 3

Verification of CGRA Executable Code and Debugging of Memory Dependence Violation CGRA可执行代码验证及内存依赖冲突调试

2012 13th International Workshop on Microprocessor Test and Verification (MTV) Pub Date : 2012-12-10 DOI: 10.1109/MTV.2012.18

H. Shim, Minwook Ahn, Jinsae Jung, Yenjo Han, Soojung Ryu

{"title":"Verification of CGRA Executable Code and Debugging of Memory Dependence Violation","authors":"H. Shim, Minwook Ahn, Jinsae Jung, Yenjo Han, Soojung Ryu","doi":"10.1109/MTV.2012.18","DOIUrl":"https://doi.org/10.1109/MTV.2012.18","url":null,"abstract":"We present verification and debugging of highly optimized executable code that is generated from C source code to run on CGRA (Coarse-Grained Reconfigurable Array). To generate the executable code, the CGRA compiler uses software pipelining technique that maps instructions in a loop body to multiple FUs (functional units) of CGRA for concurrent execution. Often, the programmer chooses to use aggressive optimization as a way to obtain highly performing executable code. For example, the programmer may turn off memory dependence check in order to suppress false dependence that would otherwise result in overly conservative, therefore poorly performing, executable code. A trouble is that it is not easy to verify correctness of the resulting executable code. In this paper, we propose a method to verify CGRA executable code and to detect memory dependence violation if there occurs such violation and to provide source code position where the violation occurs. We use the behavior of VLIW code as a reference and compare it with the behavior of CGRA code. In order to guide the comparison, compiler-generated mapping table information is used.","PeriodicalId":201401,"journal":{"name":"2012 13th International Workshop on Microprocessor Test and Verification (MTV)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132559344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Two-Way Multicasting for Test Data Compression 用于测试数据压缩的双向组播

2012 13th International Workshop on Microprocessor Test and Verification (MTV) Pub Date : 2012-12-10 DOI: 10.1109/MTV.2012.16

Lung-Jen Lee, W. Tseng, Wei-Shun Chen

引用次数: 0

Progressive-BackSpace: Efficient Predecessor Computation for Post-Silicon Debug 渐进式退格:后硅调试的高效前导计算

2012 13th International Workshop on Microprocessor Test and Verification (MTV) Pub Date : 2012-12-10 DOI: 10.1109/MTV.2012.23

Johnny J. W. Kuan, Tor M. Aamodt

{"title":"Progressive-BackSpace: Efficient Predecessor Computation for Post-Silicon Debug","authors":"Johnny J. W. Kuan, Tor M. Aamodt","doi":"10.1109/MTV.2012.23","DOIUrl":"https://doi.org/10.1109/MTV.2012.23","url":null,"abstract":"As microprocessors become more complex, finding errors in their design becomes more difficult. Most design errors are caught before the chip is fabricated, however, some make it into the fabricated design. One challenge in determining what is wrong with a new design after fabrication is the lack of observability into the state of the fabricated chip. To address this challenge, BackSpace proposes generating a trace of the states that lead up to an erroneous state. To add one state to the trace, BackSpace first generates a set of possible predecessor states (the pre-image), then tests them one at a time to find one that is reached during execution. In this paper, we propose an improved algorithm called Progressive-BackSpace. It does not enumerate every state in the pre-image. Instead, it first finds a reachable candidate state, and then determines if it is a predecessor state. This results in a practical implementation of BackSpace by greatly reducing the time needed to find prede- cessor states. The hardware overhead is also reduced by 94.4% relative to a recently proposed implementation of BackSpace. These algorithms were implemented and evaluated on a RTL model of an out-of-order processor, that models non-deterministic effects.","PeriodicalId":201401,"journal":{"name":"2012 13th International Workshop on Microprocessor Test and Verification (MTV)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134392537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1