Localization of Bugs in Processor Designs Using zamiaCAD Framework

Abstract

This paper proposes an approach to automatic localization of design errors (bugs) in processor designs based on combining statistical analysis of dynamically covered VHDL code items and static slicing. The approach considers coverage of different VHDL code items including statements, branches and conditions during processor simulation which together contribute to accurate localization of bugs. The accuracy of analysis is further improved by applying a static slicing based filter calculated by means of reference graph generation using a through-signal-assignment search from the semantically resolved elaborated models of processor designs. The localization approach has been integrated to highly scalable zamiaCAD RTL design framework. The efficiency of the proposed approach is demonstrated by applying it to debugging of an industrial processor ROBSY designed for FPGA-based test systems. The experimental results evaluate the approach for a set of real documented bug cases and the original functional test.