Dual-LFSR Reseeding for Low Power Testing

Abstract

Large test data volume and excessive test power are two strict challenges for VLSI testing. This paper presents a BIST scheme adopting dual-LFSR reseeding method to effectively reduce the amount of test data while keeping the scan-in power as low. Experimental results show that, compared with the similar work, test data volume can be significantly reduced with a roughly equal scan-in power reduction.