{"title":"低功率测试双lfsr重播","authors":"Lung-Jen Lee, W. Tseng, Wenjie. Yang","doi":"10.1109/MTV.2012.15","DOIUrl":null,"url":null,"abstract":"Large test data volume and excessive test power are two strict challenges for VLSI testing. This paper presents a BIST scheme adopting dual-LFSR reseeding method to effectively reduce the amount of test data while keeping the scan-in power as low. Experimental results show that, compared with the similar work, test data volume can be significantly reduced with a roughly equal scan-in power reduction.","PeriodicalId":201401,"journal":{"name":"2012 13th International Workshop on Microprocessor Test and Verification (MTV)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Dual-LFSR Reseeding for Low Power Testing\",\"authors\":\"Lung-Jen Lee, W. Tseng, Wenjie. Yang\",\"doi\":\"10.1109/MTV.2012.15\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Large test data volume and excessive test power are two strict challenges for VLSI testing. This paper presents a BIST scheme adopting dual-LFSR reseeding method to effectively reduce the amount of test data while keeping the scan-in power as low. Experimental results show that, compared with the similar work, test data volume can be significantly reduced with a roughly equal scan-in power reduction.\",\"PeriodicalId\":201401,\"journal\":{\"name\":\"2012 13th International Workshop on Microprocessor Test and Verification (MTV)\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 13th International Workshop on Microprocessor Test and Verification (MTV)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MTV.2012.15\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 13th International Workshop on Microprocessor Test and Verification (MTV)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTV.2012.15","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Large test data volume and excessive test power are two strict challenges for VLSI testing. This paper presents a BIST scheme adopting dual-LFSR reseeding method to effectively reduce the amount of test data while keeping the scan-in power as low. Experimental results show that, compared with the similar work, test data volume can be significantly reduced with a roughly equal scan-in power reduction.