Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems最新文献

Balancing of fault tolerance in the new version of the FERMI Channel chip: a functional evaluation 新版本FERMI通道芯片的容错平衡:功能评估

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.572031

A. Antola, L. Breveglieri

引用次数: 2

Optimising high-level synthesis for self-checking arithmetic circuits 自检算术电路的高级综合优化

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.572033

A. Antola, V. Piuri, M. Sami

引用次数: 7

Comprehensive modeling of VLSI test VLSI测试综合建模

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.572021

T. Ziaja, E. Swartzlander

引用次数: 0

Yield-performance tradeoffs for VLSI processors with partially good two-level on-chip caches 具有部分良好的两级片上缓存的VLSI处理器的产量性能权衡

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.571989

D. Nikolos, H. T. Vergos, Antonis Vazaios, Spyros Voulgaris

引用次数: 4

Tree checkers for applications with low power-delay requirements 树形检查器适用于低功耗延迟要求的应用

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.572027

C. Metra, M. Favalli, B. Riccò

引用次数: 7

A statistical parametric and probe yield analysis methodology [IC manufacture] 一种统计参数和探针良率分析方法[IC制造]

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.572012

A. Wong

{"title":"A statistical parametric and probe yield analysis methodology [IC manufacture]","authors":"A. Wong","doi":"10.1109/DFTVS.1996.572012","DOIUrl":"https://doi.org/10.1109/DFTVS.1996.572012","url":null,"abstract":"This paper describes a fast and effective parametric analysis methodology for identifying and quantifying parametric sensitivity of the product yield in a semiconductor process. Starting with over 100 parametric parameters typically, this parametric analysis methodology is able to isolate the top five parametric problems that have significant yield impact. It also able to translate the parametric problems to fab process module problems that can be fixed by fab process engineers. The proposed methodology separates the product yield into two major components: a non-random systematic yield Y/sub s/ and a random yield Y/sub r/. It calculates statistics for all ET (Electrical Test) parameters and identifies the critical yield limited factors based on the analysis of the statistical significance of the data groups. The proposed methodology is capable of determining the yield impacts of the parametric sensitive parameters, and it is also capable of identifying the causes of the parametric yield losses. Based on the results of the parametric analyses, it will propose a detail plan to improve the systematic yield. Applications of the proposed parametric and probe yield analysis methodology to many manufacturing lines' data show great success in identifying and quantifying parametric yield sensitivity.","PeriodicalId":199861,"journal":{"name":"Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125758609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

Extraction of critical areas for opens in large VLSI circuits 大型VLSI电路中关键开路区域的提取

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.571981

W. Pleskacz, C. Ouyang, Wojciech Maly

引用次数: 48

Fault probability prediction for array based designs 基于阵列设计的故障概率预测

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.571982

D. Gaitonde, Wojciech Maly, D. Walker

{"title":"Fault probability prediction for array based designs","authors":"D. Gaitonde, Wojciech Maly, D. Walker","doi":"10.1109/DFTVS.1996.571982","DOIUrl":"https://doi.org/10.1109/DFTVS.1996.571982","url":null,"abstract":"Application-specific integrated circuits (ASICs) are frequently implemented using a fixed base array personalized with metal interconnect permitting rapid turnaround. For any particular design, the array cannot be fully-utilized. Due to limitations on gate, routing, and pin resources, or the limited number of array sizes. In some array designs, such as sea-of-gates, 100% array utilization is nor possible since much of the array area will be used for routing. This partial array utilization makes yield prediction difficult. Traditional area-based yield models underestimate array yield since they assume that all defects that occur in unused portions of the array will be fatal, when most will not. Reducing the critical area by the utilization factor will overestimate yield, since some defects cause fatal circuit faults even when they occur in unused sections of the array. These yield errors can result in uncompetitive designs and lost profits. Accurate prediction of array-based ASIC yield requires an understanding of how defects interact with the base array and its personalization to cause fatal circuit faults. In this paper we describe a methodology to accurately predict the probability of fatal faults and yield in array-based ASICs using the DEFAM defect to fault mapper. We demonstrate the use of this methodology on several versions of a sea-of-gates array design, showing how traditional methods both overestimate and underestimate the actual yield.","PeriodicalId":199861,"journal":{"name":"Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"32 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124538031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Trade-offs between yield and reliability enhancement [VLSI] 良率与可靠性提升之间的权衡[VLSI]

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.571993

Arunshankar Venkataraman, I. Koren

{"title":"Trade-offs between yield and reliability enhancement [VLSI]","authors":"Arunshankar Venkataraman, I. Koren","doi":"10.1109/DFTVS.1996.571993","DOIUrl":"https://doi.org/10.1109/DFTVS.1996.571993","url":null,"abstract":"Deep sub-micron VLSI technologies have led to a large increase in the number of devices per die as well as the switching speeds. These advances have been accompanied by increased design complexity and decreasing reliability. Scaling of the device dimensions has introduced \"analog\" effects on-chip that are causing signal integrity and delay problems. These problems are not easy to estimate and reduce after the VLSI layout has been finalized for fabrication and hence new CAD techniques are being proposed to tackle this problem up-front. Similarly, vastly increased manufacturing complexities have made manufacturing costs soar, and therefore chip yields need to be increased to cut losses due to manufacturing flaws. Extensive research has been done to suggest CAD solutions for reliability and yield enhancement, but these have treated the two as disjoint issues, and raised the thought-provoking question about their relationship. In this paper, we attempt to answer this question using crosstalk minimization and yield enhancement techniques, as applied to the VLSI layout as a case study. We study the trade-offs between yield and reliability enhancement by using a weighted average of both objectives as the cost function.","PeriodicalId":199861,"journal":{"name":"Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"18 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121073490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

KITE: a behavioural approach to fault-tolerance in FPGA-based systems 基于fpga的系统中容错的行为方法

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.572040

G. Mojoli, D. Salvi, M. Sami, G. Sechi, R. Stefanelli

引用次数: 12