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Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems最新文献

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Implementing fault injection and tolerance mechanisms in multiprocessor systems 在多处理器系统中实现故障注入和容错机制
Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.572038
D. Audet, N. Gagnon, Y. Savaria
{"title":"Implementing fault injection and tolerance mechanisms in multiprocessor systems","authors":"D. Audet, N. Gagnon, Y. Savaria","doi":"10.1109/DFTVS.1996.572038","DOIUrl":"https://doi.org/10.1109/DFTVS.1996.572038","url":null,"abstract":"The size and complexity of today's multiprocessor systems require the development of new techniques to measure their dependability. An effective technique allowing one to inject faults in message passing multiprocessor systems is presented. Interrupt messages are used to trigger fault injection routines in the targeted processors. Any fault that can be emulated by a modification of the memory content of processors can be injected. That includes faults that could occur within the processors, memories and even in the communication network. The proposed technique allows one to control the time and location of faults as well as other characteristics. It has been used in a prototype multiprocessor system running real applications in order to compare the efficiency of various error detection and correction mechanisms.","PeriodicalId":199861,"journal":{"name":"Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"18 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125760177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fault detection and fault tolerance issues at CMOS level through AUED encoding 通过AUED编码的CMOS级故障检测和容错问题
Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.572032
C. Bolchini, G. Buonanno, D. Sciuto, R. Stefanelli
{"title":"Fault detection and fault tolerance issues at CMOS level through AUED encoding","authors":"C. Bolchini, G. Buonanno, D. Sciuto, R. Stefanelli","doi":"10.1109/DFTVS.1996.572032","DOIUrl":"https://doi.org/10.1109/DFTVS.1996.572032","url":null,"abstract":"A new CMOS gate structure tolerating all single transistor stuck-on faults and a large set of multiple faults is presented. Such technique is aimed at guaranteeing fault tolerance for a multiple output gate and the fault tolerance property is achieved through an AUED separated encoding of the output functions and the introduction of additional transistors which avoid fault propagation. As an example, Berger code will be discussed.","PeriodicalId":199861,"journal":{"name":"Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114589422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Redundant faults in TSC networks: definition and removal TSC网络中的冗余故障:定义与排除
Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.572034
C. Bolchini, F. Salice, D. Sciuto
{"title":"Redundant faults in TSC networks: definition and removal","authors":"C. Bolchini, F. Salice, D. Sciuto","doi":"10.1109/DFTVS.1996.572034","DOIUrl":"https://doi.org/10.1109/DFTVS.1996.572034","url":null,"abstract":"When designing Totally Self-Checking (TSC) systems the user imposes a functional encoding methodology and a constrained synthesis for guaranteeing that each fault produces a detectable error with respect to the applied coding. Both aspects, functional methodology and synthesis constraints, are not always supported by automatic tools thus possibly leading to the presence of undetected faults. The paper presents a classification of redundant faults with respect to TSC circuits (TSC redundant faults), proposing a methodology for their removal to achieve a complete fault coverage.","PeriodicalId":199861,"journal":{"name":"Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130167066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Integrated approach for circuit and fault extraction of VLSI circuits VLSI电路的集成电路与故障提取方法
Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.572002
F. Gonçalves, I. Teixeira, João Paulo Teixeira
{"title":"Integrated approach for circuit and fault extraction of VLSI circuits","authors":"F. Gonçalves, I. Teixeira, João Paulo Teixeira","doi":"10.1109/DFTVS.1996.572002","DOIUrl":"https://doi.org/10.1109/DFTVS.1996.572002","url":null,"abstract":"The purpose of this paper is to present a methodology for circuit and realistic fault extraction, and its implementation in a new tool, under development. To be included in a virtual test environment, DOTLab. Digital, analog and mixed signal ICs, implemented in CMOS, bipolar or BiCMOS technologies are handled, both in Manhattan and 45/spl deg/ geometries. For complex circuits, higher level information, obtained in the top-down design flow, is used for fault characterization. A sliding window algorithm previously used for circuit extraction, is extended for fault extraction of non-orthogonal geometries.","PeriodicalId":199861,"journal":{"name":"Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124559262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Layer reassignment for antenna effect minimization in 3-layer channel routing 三层信道路由中天线效应最小化的层重分配
Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.571996
Zhan Chen, I. Koren
{"title":"Layer reassignment for antenna effect minimization in 3-layer channel routing","authors":"Zhan Chen, I. Koren","doi":"10.1109/DFTVS.1996.571996","DOIUrl":"https://doi.org/10.1109/DFTVS.1996.571996","url":null,"abstract":"As semiconductor technology enters the deep submicron era, reliability has become a major challenge in the design and manufacturing of next generation VLSI circuits. In this paper we focus on one reliability issue-the antenna effect in the context of 3-layer channel routing. We first present an antenna effect model in 3-layer channel routing and, based on this, an antenna effect cost function is proposed. A layer reassignment approach is adopted to minimize this cost function and we show that the layer reassignment problem can be formulated as a network bipartitioning problem. Experimental results show that the antenna effect can be reduced considerably by applying the proposed technique. Compared with previous work, one advantage of our approach is that no extra channel area is required for antenna effect minimization. We show that layer reassignment technique can be used in yield-related critical area minimization in 3-layer channel routing as well. The trade-off between these two objectives is also presented.","PeriodicalId":199861,"journal":{"name":"Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123297890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Impact of physical defects on the electrical working of embedded DRAM with 0.35 /spl mu/m design rules 基于0.35 /spl mu/m设计规则的嵌入式DRAM物理缺陷对电气工作的影响
Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.572011
P. Bichebois
{"title":"Impact of physical defects on the electrical working of embedded DRAM with 0.35 /spl mu/m design rules","authors":"P. Bichebois","doi":"10.1109/DFTVS.1996.572011","DOIUrl":"https://doi.org/10.1109/DFTVS.1996.572011","url":null,"abstract":"The impact of physical defects generated by the process has been studied on embedded Dynamic Random Access Memory (DRAM) chips, with 0.35 /spl mu/m design rules. In-line automatic inspections have been performed at several steps of the process, on deposited or etched layers, with a darkfield, pixel-to-pixel comparison system. The defects detected have been systematically reviewed and characterized with an optical microscope or a scanning electron microscope (SEM) with X-ray analysis. Electrical failures have been traced back to their origin. Analysis of the correlation between physical and electrical defects has highlighted the main causes of yield loss. Moreover, the physical defects have been subdivided into classes associated with different types of failure, thus enabling the yield to be predicted during the process.","PeriodicalId":199861,"journal":{"name":"Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114084781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Fault tolerant Newton-Raphson dividers using time shared TMR 使用分时TMR的容错牛顿-拉夫森分频器
Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.572030
W. Gallagher, E. Swartzlander
{"title":"Fault tolerant Newton-Raphson dividers using time shared TMR","authors":"W. Gallagher, E. Swartzlander","doi":"10.1109/DFTVS.1996.572030","DOIUrl":"https://doi.org/10.1109/DFTVS.1996.572030","url":null,"abstract":"The Newton-Raphson method is a popular means of performing division on modern processors, as it can utilize the multiplication hardware already on chip and converge quickly to a solution. However, high-precision multiplications are not required for the early iterations of the algorithm. Furthermore, rounding the quotient by computing the inverse function may not require a full precision computation. By using a smaller multiplier when less precision is required, and using the same multiplier with feedback paths when more precision is required, a smaller, and sometimes faster, divider can be realized. This approach lends itself to time shared triple modular redundancy, where space is saved over traditional TMR with a reasonable penalty to latency.","PeriodicalId":199861,"journal":{"name":"Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123483596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults 带PE和总线故障的1 1/2轨道开关网格阵列的重构
Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.572041
T. Horita, I. Takanami
{"title":"Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults","authors":"T. Horita, I. Takanami","doi":"10.1109/DFTVS.1996.572041","DOIUrl":"https://doi.org/10.1109/DFTVS.1996.572041","url":null,"abstract":"The mesh-connected processor array model using 1 1/2 track-switches has an advantage of its inherent simplicity of the routing hardware. In this paper, for the model, we investigate its fault tolerant ability for simultaneous processor element (PE) and bus faults. First, we discuss how interconnections are restructured, avoiding faulty PE and buses. Then, we present a neural algorithm for reconfiguration, using a Hopfield-type neural network model. We show the influence of bus faults on the reliabilities of arrays by simulation. The proposed neural algorithm has an advantage that the computation time for reconstruction is so small. Furthermore, the algorithm has a potentiality that a built-in self-reconfigurable system may be realized by implementing the algorithm by hardware in a less complicated way.","PeriodicalId":199861,"journal":{"name":"Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125375784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Maximum likelihood estimation for yield analysis [IC manufacture] 成品率分析的最大似然估计[集成电路制造]
Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.572019
F. Ferguson, Jianlin Yu
{"title":"Maximum likelihood estimation for yield analysis [IC manufacture]","authors":"F. Ferguson, Jianlin Yu","doi":"10.1109/DFTVS.1996.572019","DOIUrl":"https://doi.org/10.1109/DFTVS.1996.572019","url":null,"abstract":"This paper presents an iterative maximum likelihood (ML) estimation method for statistical analysis of yield loss. By means of Inductive Fault Analysis (IFA) and circuit simulation, the mapping between defect types to the corresponding fault signature is constructed. Using the count of each fault signature occurrence, which is provided by a tester, the most likely causes of low yield are identified automatically without the need for physically deprocessing the defective ICs. We show that our method is superior to current practices for yield analysis which use a least squares fit or partial tester data to estimate defect densities.","PeriodicalId":199861,"journal":{"name":"Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117179800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reliable logic circuits with byte error control codes-a feasibility study 具有字节错误控制码的可靠逻辑电路的可行性研究
Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 1996-11-06 DOI: 10.1109/DFTVS.1996.572035
Jien-Chung Lo, M. Kitakami, E. Fujiwara
{"title":"Reliable logic circuits with byte error control codes-a feasibility study","authors":"Jien-Chung Lo, M. Kitakami, E. Fujiwara","doi":"10.1109/DFTVS.1996.572035","DOIUrl":"https://doi.org/10.1109/DFTVS.1996.572035","url":null,"abstract":"This paper addresses the relations between logic circuit synthesis, error model and error control codes so that the efficient reliable logic circuits can be obtained. We propose that single fault masking capability of a random logic circuit can be obtained by encoding its outputs in a byte error correcting code; this is equivalent to that of the triple module redundancy (TMR) technique. Similarly, byte error detecting code can be used to provide an equivalence of duplication. In this paper, we address the problems and issues related to the realization of byte-organized configuration where the byte error control codes can be applied. Some MCNC benchmark circuits are used as examples to demonstrate the feasibility of the proposed concept.","PeriodicalId":199861,"journal":{"name":"Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124083929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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