Optimising high-level synthesis for self-checking arithmetic circuits

A. Antola, V. Piuri, M. Sami
{"title":"Optimising high-level synthesis for self-checking arithmetic circuits","authors":"A. Antola, V. Piuri, M. Sami","doi":"10.1109/DFTVS.1996.572033","DOIUrl":null,"url":null,"abstract":"Introduction of self-checking capacity in arithmetic systems since the initial steps of high-level synthesis is taken into account, as an alternative to conventional solutions that adopt ad-hoc coding or comparable techniques after the register-level architecture has been fully defined. A technique based on initial partitioning of the Data Flow Graph into detectable subgraphs is proposed, by which all single errors appearing within one subgraph are detected; an algorithm leading to optimize resource sharing (allocation and binding of both functional units and registers) while keeping minimum latency and optimum number of checkers is discussed.","PeriodicalId":199861,"journal":{"name":"Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1996.572033","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

Abstract

Introduction of self-checking capacity in arithmetic systems since the initial steps of high-level synthesis is taken into account, as an alternative to conventional solutions that adopt ad-hoc coding or comparable techniques after the register-level architecture has been fully defined. A technique based on initial partitioning of the Data Flow Graph into detectable subgraphs is proposed, by which all single errors appearing within one subgraph are detected; an algorithm leading to optimize resource sharing (allocation and binding of both functional units and registers) while keeping minimum latency and optimum number of checkers is discussed.
自检算术电路的高级综合优化
考虑到自高级综合的初始步骤以来在算术系统中引入自检能力,作为在寄存器级架构完全定义后采用特设编码或类似技术的传统解决方案的替代方案。提出了一种基于数据流图初始划分为可检测子图的技术,该技术可以检测出一个子图中出现的所有单个错误;讨论了一种优化资源共享(功能单元和寄存器的分配和绑定)同时保持最小延迟和最优检查器数量的算法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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