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ESSCIRC '88: Fourteenth European Solid-State Circuits Conference最新文献

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Design of a PLU (Programmable Logic Unit), a new block for signal processing 可编程逻辑单元(PLU)的设计，一种新的信号处理模块
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468447
P. de Bakker, A. Delaruelle, B. De Loore
{"title":"Design of a PLU (Programmable Logic Unit), a new block for signal processing","authors":"P. de Bakker, A. Delaruelle, B. De Loore","doi":"10.1109/ESSCIRC.1988.5468447","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468447","url":null,"abstract":"In this paper a new building block is described which can be used in Digital Signal Processing (DSP) IC's. This module, the PLU (Programmable Logic Unit), can perform dyadic operations (A v B, A ^ B, A © B ...), monadic operations (¿A, ¿B , pass shiftr, ...) and bitwise operations (mask, scramble, ...). Furthermore, bitwise operations can be combined with monadic or dyadic operations. The PLU is easy to program as it is possible for users to define their own instruction set. In addition it is very effective with respect to area and speed. In order to make a flexible PLU, a parametrised module generator has been written. For a typical instance the total chip area necessary for an 8 bits PLU is 0.16 mm2 in a 1.6 ¿m process. The delay of the PLU equals a two gate propagation delay.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115959970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Performance Enhancement of Compatible Lateral Bipolar Transistors for High-Precision CMOS Analog Design 用于高精度CMOS模拟设计的兼容侧双极晶体管的性能提升
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468282
X. Arreguit, E. Vittoz
{"title":"Performance Enhancement of Compatible Lateral Bipolar Transistors for High-Precision CMOS Analog Design","authors":"X. Arreguit, E. Vittoz","doi":"10.1109/ESSCIRC.1988.5468282","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468282","url":null,"abstract":"The residual gate effect on the lateral collector current of compatible lateral bipolar transistors is modelled and a novel method for biasing the gate is presented. It is shown that this effect can be used to compensate transistors mismatch in order to enhance the precision of analog CMOS circuits by a factor of 5-10 over a temperature range of 100°K.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116295641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of a Compiler for the Generation of Self-Testable Macros 用于生成自测试宏的编译器设计
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468351
R.P. van Riessen, H. Kerkhoff, A. Kloppenburg
{"title":"Design of a Compiler for the Generation of Self-Testable Macros","authors":"R.P. van Riessen, H. Kerkhoff, A. Kloppenburg","doi":"10.1109/ESSCIRC.1988.5468351","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468351","url":null,"abstract":"This paper describes the design and implementation of a macro-dependent self-test compiler. The compiler requires information from the designer about the type and size of the macro that has to be generated. Dependent on the desired faultcoverage, the compiler automatically generates the layout of the macro, including the appropriate data-generation and evaluation self-test hardware. A scan path, based on the boundary-scan principle, is used to initialize the self-test hardware.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116404990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fast CMOS Amplifiers for High-Frequency Switched-Capacitor Circuits 用于高频开关电容电路的快速CMOS放大器
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468383
F. Dorel, P. Molliet, F. Krummenacher, M. Declercq
{"title":"Fast CMOS Amplifiers for High-Frequency Switched-Capacitor Circuits","authors":"F. Dorel, P. Molliet, F. Krummenacher, M. Declercq","doi":"10.1109/ESSCIRC.1988.5468383","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468383","url":null,"abstract":"A new approach for the optimization of high-speed amplifiers dedicated to SC integrators is presented. Inverter-based pseudo-differential structures are shown to be well-suited to high speed applications. The problem of their inherently poor PSRR is solved by an on-chip low-area voltage regulator. An algorithmic method developed for the computer-aided synthesis of the amplifier is described. Experimental results are presented for a SC filter with a 5MHz cut-off frequency at 50 Mhz sampling. PSSR performance and validity of the automatic dimensioning are finally discussed.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123078715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Development of a New Type of Self-Scanned Electron Image Sensing Integrated Circuit 一种新型自扫描电子图像传感集成电路的研制
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468263
J. Hatfield, T. York, P. Hicks, J. Comer
{"title":"Development of a New Type of Self-Scanned Electron Image Sensing Integrated Circuit","authors":"J. Hatfield, T. York, P. Hicks, J. Comer","doi":"10.1109/ESSCIRC.1988.5468263","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468263","url":null,"abstract":"The object of this research was to design and fabricate a linear array of electron sensing electrodes coupled to detection and read-out circuitry in the form of amplifiers and counters integrated onto a single CMOS chip. The chip replaces existing position-sensitive detection systems in electron spectrometers.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128112712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
1M-bit Multi-port RAM for High-resolution Graphics 用于高分辨率图形的1m位多端口RAM
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468426
Y. Yamaguchi, K. Satoh, N. Taninura, K. Inoue
{"title":"1M-bit Multi-port RAM for High-resolution Graphics","authors":"Y. Yamaguchi, K. Satoh, N. Taninura, K. Inoue","doi":"10.1109/ESSCIRC.1988.5468426","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468426","url":null,"abstract":"INTRODUCTION A lM-bit nulti-port RAM has been developed for high-resolution graphics where compact size, high speed and capacity are important. This device is divided into a 256K words x 4-bit RAM port and a 512 x 4-bit Serial Access Memory (SAM) port. The RAM port performs standard Dynamic RAM operations, logic operations, special data transfer operations, and flash write operations. The SAM port with 2,048-bit double data registers inputs or outputs the data in a serial order. The RAM port and the SAM port can operate asynchronously. This paper describes the circuit designs that permit a small chip size and new optional functions (special read data transfer and flash write), and the electrical characteristics.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127269923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Digital Controlled Oscillator 数字控制振荡器
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468292
B. Giebel, J. Lutz, P. O'Leary
{"title":"Digital Controlled Oscillator","authors":"B. Giebel, J. Lutz, P. O'Leary","doi":"10.1109/ESSCIRC.1988.5468292","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468292","url":null,"abstract":"A monolithically integrated, digitally controlled oscillator is presented. It has an output frequency range from 18.9 Hz to ≫ 20 MHz, the long term stability of a quartz oscillator and a short term clock edge uncertainty with a standard deviation of 0.4 ns. The digital frequency control is fully linear with a resolution of 18.9 Hz. The only required external component is a reference quartz. The circuit operates from a single 5 V power supply and is fabricated in a 1.5 ¿m, double metal, single poly, CMOS process. The chip area is 4.1 mm2.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127236437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 100 ns 4Mbit (512K×8bit) CMOS EPROM 一个100 ns 4Mbit (512K×8bit) CMOS EPROM
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468475
M. Kamaya, M. Higuchi, T. Urai, K. Ninomiya, T. Watanabe, S. Koyama, T. Jinbo
{"title":"A 100 ns 4Mbit (512K×8bit) CMOS EPROM","authors":"M. Kamaya, M. Higuchi, T. Urai, K. Ninomiya, T. Watanabe, S. Koyama, T. Jinbo","doi":"10.1109/ESSCIRC.1988.5468475","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468475","url":null,"abstract":"This paper describes a high speed 4M bit CMOS EPROM with 100 ns access time, 512K × 8 bit organization, and 40 ¿s/word programing time. Polycide word lines, optimization of sense amplifier gain and anti-noise output buffer design are essential to shorten the access time. The chip is fabricated in 1.0 ¿m Nwell CMOS technology with double poly, single silicide, and single metal. To obtain pattern shrinkage, plugged contact structure is used. The chip size of 5.48 mm × 14.79 mm is accomplished.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"313 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116119605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1-Mbit BiCMOS DRAM using Temperature Compensation Circuit Techniques 采用温度补偿电路技术的1mbit BiCMOS DRAM
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468465
G. Kitsukawa, K. Itoh, R. Hori, Y. Kawajiri, Takao Watanabe, T. Kawahara, Tetsuro Matsumoto, Y. Kobayashi
{"title":"A 1-Mbit BiCMOS DRAM using Temperature Compensation Circuit Techniques","authors":"G. Kitsukawa, K. Itoh, R. Hori, Y. Kawajiri, Takao Watanabe, T. Kawahara, Tetsuro Matsumoto, Y. Kobayashi","doi":"10.1109/ESSCIRC.1988.5468465","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468465","url":null,"abstract":"A temperature-compensation circuit technique for a dynamic random-access memory (DRAM) with an on-chip voltage limiter is evaluated using a 1-Mb BiCMOS DRAM. It was found that a BiCMOS bandgap reference generator scheme yields an internal voltage immune from temperature and V/sub cc/ variation. Also, bipolar-transistor-oriented memory circuits, such as a static BiCMOS word driver, improve delay time at high temperatures. Furthermore, the BiCMOS driver proves to have better temperature characteristics than the CMOS driver. Finally, a 1-Mb BiCMOS DRAM using the proposed technique was found to have better temperature characteristics than the 1-Mb CMOS DRAM which uses similar techniques, as was expected. Thus, BiCMOS DRAMs have improved access time at high temperatures compared with CMOS DRAMs. >","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116064167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
ECIPS/DAQ: A Transistor Modelling Environment ECIPS/DAQ:一个晶体管建模环境
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468287
J. P. Drazin, A. M. Barnard
{"title":"ECIPS/DAQ: A Transistor Modelling Environment","authors":"J. P. Drazin, A. M. Barnard","doi":"10.1109/ESSCIRC.1988.5468287","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468287","url":null,"abstract":"A general purpose transistor measurement and characterisation system for the development of compact device models is described. The environment comprises a measurement (DAQ) and a parameter extraction (ECIPS) system used in conjunction with a commercial relational database management system (RDBMS).","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"17 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132347428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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