{"title":"用于高精度CMOS模拟设计的兼容侧双极晶体管的性能提升","authors":"X. Arreguit, E. Vittoz","doi":"10.1109/ESSCIRC.1988.5468282","DOIUrl":null,"url":null,"abstract":"The residual gate effect on the lateral collector current of compatible lateral bipolar transistors is modelled and a novel method for biasing the gate is presented. It is shown that this effect can be used to compensate transistors mismatch in order to enhance the precision of analog CMOS circuits by a factor of 5-10 over a temperature range of 100°K.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Performance Enhancement of Compatible Lateral Bipolar Transistors for High-Precision CMOS Analog Design\",\"authors\":\"X. Arreguit, E. Vittoz\",\"doi\":\"10.1109/ESSCIRC.1988.5468282\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The residual gate effect on the lateral collector current of compatible lateral bipolar transistors is modelled and a novel method for biasing the gate is presented. It is shown that this effect can be used to compensate transistors mismatch in order to enhance the precision of analog CMOS circuits by a factor of 5-10 over a temperature range of 100°K.\",\"PeriodicalId\":197244,\"journal\":{\"name\":\"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1988.5468282\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1988.5468282","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Performance Enhancement of Compatible Lateral Bipolar Transistors for High-Precision CMOS Analog Design
The residual gate effect on the lateral collector current of compatible lateral bipolar transistors is modelled and a novel method for biasing the gate is presented. It is shown that this effect can be used to compensate transistors mismatch in order to enhance the precision of analog CMOS circuits by a factor of 5-10 over a temperature range of 100°K.