2013 International conference on Circuits, Controls and Communications (CCUBE)最新文献_第2页

Cluster based human action recognition using latent dirichlet allocation 基于潜在狄利克雷分配的聚类人体动作识别

2013 International conference on Circuits, Controls and Communications (CCUBE) Pub Date : 2013-12-01 DOI: 10.1109/CCUBE.2013.6718561

N. Deepak, R. Hariharan, U. Sinha

引用次数: 3

Analyzing thermal runaway in semiconductor devices using the constrained method of optimization 用约束优化方法分析半导体器件的热失控

2013 International conference on Circuits, Controls and Communications (CCUBE) Pub Date : 2013-12-01 DOI: 10.1109/CCUBE.2013.6718563

V. Lakshminarayanan, N. Sriraam

引用次数: 2

ASIC implementation of fuzzy-PID controller for aircraft roll control 飞机滚转模糊pid控制器的ASIC实现

2013 International conference on Circuits, Controls and Communications (CCUBE) Pub Date : 2013-12-01 DOI: 10.1109/CCUBE.2013.6718551

Subash John, A. Rasheed, V. K. Reddy

引用次数: 12

Design and real time performance evaluation of islanding and load shedding scheme 孤岛减载方案的设计与实时性能评价

2013 International conference on Circuits, Controls and Communications (CCUBE) Pub Date : 2013-12-01 DOI: 10.1109/CCUBE.2013.6718567

K. Meera, J. Sreedevi, Kondalarao Bavisetti, Umamaheswarrao

{"title":"Design and real time performance evaluation of islanding and load shedding scheme","authors":"K. Meera, J. Sreedevi, Kondalarao Bavisetti, Umamaheswarrao","doi":"10.1109/CCUBE.2013.6718567","DOIUrl":"https://doi.org/10.1109/CCUBE.2013.6718567","url":null,"abstract":"Industrial plant units are to be isolated from the grid as quickly as possible during grid disturbances. After islanding, load shedding is one the main actions that can be taken to prevent complete black out in industrial plants during such disturbances. The challenge for the islanding scheme is to island within the critical clearing time to avoid total system collapse. Islanding should not be done for every temporary disturbance in the grid as frequent islanding will reduce the reliability of the system. For sensing such conditions, careful selection of settings of the protective devices such as under frequency relay, over frequency relay, ±df/dt -rate of change of frequency relay, undervoltage and directional over current relays is required. Composite Islanding Load Management System (CILMS) implementing the logics for islanding and load shedding can be pre-commissioned and tuned, while connected to the Real Time Digital Simulator (RTDS) in a closed loop. In this paper, the results of the studies which formed the basis for arriving at the settings to be implemented in CILMS and performance evaluation of CILMS on Real Time Digital Simulator (RTDS) which helped in fine tuning the settings for a practical system are discussed.","PeriodicalId":194102,"journal":{"name":"2013 International conference on Circuits, Controls and Communications (CCUBE)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131829552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Fuzzy edge detector based blocking artifacts removal of DCT compressed images 基于模糊边缘检测器的DCT压缩图像块化伪影去除

2013 International conference on Circuits, Controls and Communications (CCUBE) Pub Date : 2013-12-01 DOI: 10.1109/CCUBE.2013.6718544

D. Gambhir, N. Rajpal

引用次数: 7

A high speed low noise CMOS dynamic full adder cell 一种高速低噪声CMOS动态全加法器单元

2013 International conference on Circuits, Controls and Communications (CCUBE) Pub Date : 2013-12-01 DOI: 10.1109/CCUBE.2013.6718575

P. Meher, K. Mahapatra

引用次数: 9

Novel multilevel inverter with reduced number of switches and batteries 新型多电平逆变器，减少了开关和电池的数量

2013 International conference on Circuits, Controls and Communications (CCUBE) Pub Date : 2013-12-01 DOI: 10.1109/CCUBE.2013.6718565

R. Deepak, Vishnu S. Kasturi, Lepakshi Sarkar, Y. Manjunatha, B. Lakshmikantha

{"title":"Novel multilevel inverter with reduced number of switches and batteries","authors":"R. Deepak, Vishnu S. Kasturi, Lepakshi Sarkar, Y. Manjunatha, B. Lakshmikantha","doi":"10.1109/CCUBE.2013.6718565","DOIUrl":"https://doi.org/10.1109/CCUBE.2013.6718565","url":null,"abstract":"Design of an inverter has evolved from simple two leveled output to complex multi level output in the recent years. With the demand for high power inverter unit, multilevel inverters have been attracting extensive attention from academia as well as industry. Among the best-known topologies are the H-bridge cascade inverter, the capacitor clamping inverter and the diode clamping inverter. The significant advantages of multilevel configuration are voltage sharing both statical ly and dynamically and it produces better voltage waveforms with less harmonic contents. A conventional multilevel inverter requires `n' DC sources to obtain 2n + 1 output voltage levels. One particular disadvantage is, it increases greater number of power semiconductor switches. This paper proposes a new concept of switching with reduced number of switches and batteries. This concept helps to reduce the complexity of switching compared to other conventional methods and DC Link counterparts. Proposed multilevel inverter having seven level output is experimentally validated with a simple resistive load.","PeriodicalId":194102,"journal":{"name":"2013 International conference on Circuits, Controls and Communications (CCUBE)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133220918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A novel 6 to 14 GHz. thin radar absorber based on circular resistive patch FSS 新颖的6到14 GHz。基于圆形电阻贴片FSS的薄型雷达吸收器

2013 International conference on Circuits, Controls and Communications (CCUBE) Pub Date : 2013-12-01 DOI: 10.1109/CCUBE.2013.6718574

Chandrika Sudhendra, A. Pillai, A. Madhu, K. Rao

引用次数: 8

Design of a low noise PLL for GSM application GSM低噪声锁相环的设计

2013 International conference on Circuits, Controls and Communications (CCUBE) Pub Date : 2013-12-01 DOI: 10.1109/CCUBE.2013.6718578

U. Nanda, D. P. Acharya, S. K. Patra

引用次数: 13

FPGA implementation of blob detection algorithm for object detection in visual navigation 用于视觉导航目标检测的blob检测算法的FPGA实现

2013 International conference on Circuits, Controls and Communications (CCUBE) Pub Date : 2013-12-01 DOI: 10.1109/CCUBE.2013.6718570

D. Kiran, A. Rasheed, Hariharan Ramasangu

{"title":"FPGA implementation of blob detection algorithm for object detection in visual navigation","authors":"D. Kiran, A. Rasheed, Hariharan Ramasangu","doi":"10.1109/CCUBE.2013.6718570","DOIUrl":"https://doi.org/10.1109/CCUBE.2013.6718570","url":null,"abstract":"Visual navigation system is widely used in various applications such as traffic surveillance, guidance of autonomous vehicles etc. Object detection is one of the important steps which identifies obstacle and provides information about obstacle's location in the image scenario. Blob detection method has been chosen to detect object and to extract required information about the object. Implementation of blob detection algorithm on FPGA requires more hardware resources in terms of number for logic gates etc. In this paper, a modification has been proposed for effective hardware implementation of centroid and area computations while using blob detection algorithm. The proposed approach utilizes a novel way to label the connected components and leads to effective hardware implementation. The proposed algorithm utilizes fewer resources and takes less computational time. This algorithm has been implemented in Xilinx Virtex V FPGA board which operates at 100MHz. Processing time taken by the algorithm for computing area and centroid of objects along with labeling is 0.22ms for image resolution of 100 × 100. Algorithm utilizes 4% of available hardware resource and 4 block RAM for complete processing.","PeriodicalId":194102,"journal":{"name":"2013 International conference on Circuits, Controls and Communications (CCUBE)","volume":"302 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132859547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9