Design of a low noise PLL for GSM application

Abstract

This paper explores a Phase Locked Loop (PLL) design that can satisfy a wide range of frequency which can be used for GSM application. PLL is used for the wireless communication in the GHz range to correct the phase and frequency error and provides synchronization with low locking time, reduced skew and jitter. The PLL is used inside many processing elements to provide clock synchronization and clock recovery. Above important applications call for the design of a Phase Locked Loop with low phase noise, low lock in time and high capture range. The design of this PLL is performed in 90nm process technology (GPDK 090) in cadence virtuoso Analog design environment which achieves a frequency range of 250 MHz to 950 MHz. This PLL has phase noise of -91.74 dBc/ Hz at 1 MHz of offset frequency where the lock in time is 220 ns which is considerably less.