2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)最新文献_第3页

Comparative Analysis of different Machine Learning Classifiers for Prediction of Diabetic Retinopathy 不同机器学习分类器预测糖尿病视网膜病变的比较分析

2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2021-08-27 DOI: 10.1109/RTEICT52294.2021.9573525

R. Priyanka, J. Aravinth

引用次数: 3

Vertical Scaling of Virtual Machines In Cloud Environment 云环境下虚拟机的垂直扩展

2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2021-08-27 DOI: 10.1109/RTEICT52294.2021.9573715

Karunakar Rai, B. Sahana, Akshay Narayan Pai, S. Gautham, U. Dhanush

{"title":"Vertical Scaling of Virtual Machines In Cloud Environment","authors":"Karunakar Rai, B. Sahana, Akshay Narayan Pai, S. Gautham, U. Dhanush","doi":"10.1109/RTEICT52294.2021.9573715","DOIUrl":"https://doi.org/10.1109/RTEICT52294.2021.9573715","url":null,"abstract":"Virtual Machine (VM) scaling in cloud is a common technique followed in cloud infrastructures to efficiently make use of the VM instances to get more throughput. There are two major scaling approaches which are being followed these days namely Horizontal Scaling and Vertical Scaling. The horizontal scaling is widely used as compared to the vertical scaling due to its ease of implementation and profit measure whereas the implementation of vertical scaling is more complex. The Vertical Scaling is accomplished using the Hypervisor tool - Virtual Box. We make use of the CLI provided by the Virtual Box to vertically scale the VMs. Python script is written to take care of all the edge cases that could be encountered in the vertical VM scaling. In addition to this, user activity statistics are logged to the database accompanying with the changes to the allotted VMs. A web interface is provided to the user/administrator to keep track of the changes in the VM environment in different user sessions. Scaling of different VM parameters like RAM & VRAM size, Usage of number of CPUs and Availability of different audio controller types are discussed in this paper. This paper proposes a cost effective method to implement vertical scaling of VM in cloud architecture.","PeriodicalId":191410,"journal":{"name":"2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131733109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comparison of Power Dissipation for CMOS and FinFET Dependent 6T SRAM at 18 nm Technology 基于CMOS和FinFET的6T SRAM在18nm工艺下的功耗比较

2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2021-08-27 DOI: 10.1109/RTEICT52294.2021.9573749

M. Govinda, RAVISH ARADHYA H V

{"title":"Comparison of Power Dissipation for CMOS and FinFET Dependent 6T SRAM at 18 nm Technology","authors":"M. Govinda, RAVISH ARADHYA H V","doi":"10.1109/RTEICT52294.2021.9573749","DOIUrl":"https://doi.org/10.1109/RTEICT52294.2021.9573749","url":null,"abstract":"The requirement for low-power high-thickness gadgets has added to consistent MOSFET scaling. Nonetheless, assortment of troubles owing to the semiconductor size scaling, for example, SCEs and edge voltage move off concerns. FinFET is one of the options in contrast to MOSFET's numerous entryway FET to settle SCEs and improve effectiveness. As it is consistent with the continuous MOSFET producing innovations and disentangled in structure, the vast majority of the applications supplant conventional MOSFET. Recollections Specifically Static Random Access Memories One of the manners by which FinFETs can be utilized is (SRAMs). The force dissemination investigation utilizing FinFETs and MOSFET for 6T SRAM is talked about in this article. Since high thickness and low spillage recollections are required, the utilization of FinFETs for SRAM configuration is generally fitting. The channel is wrapped with a three-sided entryway that diminishes the corruption of versatility because of the cross over electric field. Since the door has awesome channel control, we can utilize low voltage supply for SRAM administration, bringing about force scattering reduction.90% of the force dispersal is diminished utilizing FinFET based 6T SRAM.","PeriodicalId":191410,"journal":{"name":"2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122977164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Energy Efficient Beamforming for 5G 5G的高能效波束成形

2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2021-08-27 DOI: 10.1109/RTEICT52294.2021.9573748

Sindhu Bagal, Vaishnavi Hayagreev, Shivani Nazare, Tatpada Raikar, Parikshit Hegde

{"title":"Energy Efficient Beamforming for 5G","authors":"Sindhu Bagal, Vaishnavi Hayagreev, Shivani Nazare, Tatpada Raikar, Parikshit Hegde","doi":"10.1109/RTEICT52294.2021.9573748","DOIUrl":"https://doi.org/10.1109/RTEICT52294.2021.9573748","url":null,"abstract":"One of the most challenging aspects of implementing 5G communication technology is determining the best beamforming technique. In this paper, the performance of beamforming has been simulated for varying design parameters. 5th Generation (5G) data services will usher in the next generation of mobile networks. Speeds of more than 10 Gbps will be possible with the 5G system. In order to implement this super data rate, a few major problems must be solved. Beam forming is one of them, basically to direct the beam in a particular direction towards the intended user. This project involves designing an antenna array and testing it using a channel model to achieve beam formation. The main goal is to increase the obtained power by making the beam more energy efficient. The antenna is designed as a rectangular microstrip patch antenna array with unique design parameters to improve beam directivity, F/B ratio, received power, and its overall efficiency. This research shows that as the number of antenna elements increase and design parameters are optimized the directivity, F/B ratio, and received power improve.","PeriodicalId":191410,"journal":{"name":"2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122997887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Performance Evaluation of Graph Partitioning on Many-core System 多核系统图划分的性能评价

2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2021-08-27 DOI: 10.1109/RTEICT52294.2021.9573598

A. Tapase, Siddheshwar V. Patil, D. Kulkarni

引用次数: 0

Conflict Management of Multi Modal RFID in Asset Tracking 多模态RFID在资产跟踪中的冲突管理

2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2021-08-27 DOI: 10.1109/RTEICT52294.2021.9573819

Sumalatha Aradhya, K. N. Pramod, P. Rudraradhya, B. Kiran, G. Kotresh

{"title":"Conflict Management of Multi Modal RFID in Asset Tracking","authors":"Sumalatha Aradhya, K. N. Pramod, P. Rudraradhya, B. Kiran, G. Kotresh","doi":"10.1109/RTEICT52294.2021.9573819","DOIUrl":"https://doi.org/10.1109/RTEICT52294.2021.9573819","url":null,"abstract":"Inventory management is the soul of manufacturing industry. The inventories must be tracked and controlled remotely by the owner. But, handling multiple assets with RFID sensor at a time is a challenging job. The conflict in reading the RFID tags in synchronous mode must be managed effectively. Legacy application that uses the old RFID tag may become obsolete and need replacement by new tags. The existing approach to detect the legacy RFID tags such as IEC 15693 with mode 1 protocol is not working with new RFID readers and hence is incompatible. We are proposing a solution to make the passive legacy RFID tags as to make active and detectable using any RFID reader. The proposed solution shall help the assets with legacy RFID tags as traceable and controllable by the remote application automatically. The conflict resolution hypothesis is derived as part of the research work and an IoT based application is written to test the use of algorithm. The assets that are leading to conflicts are identified and after the conflict rectification, both passive and active RFID tags are getting identified successfully. The data is processed through AWS cloud and analyzed to control the multi modal sensors remotely.","PeriodicalId":191410,"journal":{"name":"2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122192216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Designing, Analysis and Synthesis of 32-Bit Configurable Hack CPU 32位可配置破解CPU的设计、分析与综合

2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2021-08-27 DOI: 10.1109/RTEICT52294.2021.9573593

Ruchita Kawle, S. Thakare

{"title":"Designing, Analysis and Synthesis of 32-Bit Configurable Hack CPU","authors":"Ruchita Kawle, S. Thakare","doi":"10.1109/RTEICT52294.2021.9573593","DOIUrl":"https://doi.org/10.1109/RTEICT52294.2021.9573593","url":null,"abstract":"Designing of a configurable/modular processor based on HACK computer architecture is presented in the paper. The process confused in designing and building compound circuit of computer system that can perform real world computation is explained in the paper. The processor is build using bottom up approach; that is designing from basic components to major components like PC, ALU, ROM, RAM.A configurable processor signifies a processor that is configurable with respect to memory and components. Configurable memory denotes processor memory with 16 bit, 32 bit, 64 bit according to the requirement. And configurable components are in the sense that any specific individual component can be swapped with any other particular component according to the need and can analyze the performance change. The simulation of design is performed on Modelsim -Altera 10.1d (Quartus II 13.0sp1). The analysis and synthesis based on various parameters (i.e area/device utilization, Minimum propagation delay, Maximum frequency, Throughput, RTL schematic, Technology schematic) is done on Quartus II 13.0sp1.","PeriodicalId":191410,"journal":{"name":"2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114223454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermal image enhancement using kurtosis based clipping histogram method 基于峰度的剪切直方图方法增强热图像

2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2021-08-27 DOI: 10.1109/RTEICT52294.2021.9573576

M. Tirupathamma, V. Niranjan

{"title":"Thermal image enhancement using kurtosis based clipping histogram method","authors":"M. Tirupathamma, V. Niranjan","doi":"10.1109/RTEICT52294.2021.9573576","DOIUrl":"https://doi.org/10.1109/RTEICT52294.2021.9573576","url":null,"abstract":"Enhancement is necessary to improve the visibility of the thermal or infrared images useful in the surveillance applications. As the thermal images will suffer with poor visibility, low contrast and low resolution it is difficult to enhance. In this paper, two new approaches are introduced for increasing the visibility of the low illumination thermal infrared images. The first method is based on the Histogram matching technique. The histogram of the low illumination input image is modified in accordance with the statistical parameters of reference image. Second approach is based on clipping the histogram using kurtosis and then bisecting the histogram using the median. For performance evaluation few images from OSU thermal dataset are used and compared with existing methods. The proposed technique performance is evaluated using various quality metrics such as PSNR, SSIM, Entropy and Absolute Mean Brightness Error (AMBE). The results have shown the improvement in the PSNR, SSIM and AMBE when compared with the mean based clipping. The performance of the proposed methods gave improved quantitative parameters in comparison with the state of the art methods.","PeriodicalId":191410,"journal":{"name":"2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120956976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Power Efficient and High-performance 4-bit Dadda Multiplier using Multiplexer based BEC-1 converter 采用基于bec1转换器的多路复用器的高效节能4位数据乘法器

2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2021-08-27 DOI: 10.1109/RTEICT52294.2021.9573750

S. Prasad, S. K. Sinha

{"title":"Power Efficient and High-performance 4-bit Dadda Multiplier using Multiplexer based BEC-1 converter","authors":"S. Prasad, S. K. Sinha","doi":"10.1109/RTEICT52294.2021.9573750","DOIUrl":"https://doi.org/10.1109/RTEICT52294.2021.9573750","url":null,"abstract":"Recently, the demand for low power electronic devices with fast device performance has increased. Low power consumption makes the device portable and extends its service life. In this work, the dadda multiplier is designed using the traditional energy-saving adder with cmos technology. The dadda multiplier has become the most popular tree multiplier due to its high computational speed and low hardware configuration. Most of the delay of the dadda multiplier depends on the partial and final sum of the product. Energy-saving full adders and half adders are used to reduce the total power requirement of the dadda multiplier. The dadda multiplier uses modified adder design and is compared to traditional cmos adder. The two designs are computed by using with and without partitioning the technique. The power and delay of each dadda multiplier are analyzed using the Tanner EDA tool. The analysis of the expected results shows that the partitioned multiplier with conventional and modified full adder logic works better than the unpartitioned multiplier with conventional and modified full adder.","PeriodicalId":191410,"journal":{"name":"2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121051208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Serverless Computing and the Emergence of Function-as-a-Service 无服务器计算和功能即服务的出现

2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Pub Date : 2021-08-27 DOI: 10.1109/RTEICT52294.2021.9573962

Rishabh Patil, Tanveesh Singh Chaudhery, Muhammad Ali Qureshi, Vinaya Sawant, Harshal Dalvi

引用次数: 1