Power Efficient and High-performance 4-bit Dadda Multiplier using Multiplexer based BEC-1 converter

Abstract

Recently, the demand for low power electronic devices with fast device performance has increased. Low power consumption makes the device portable and extends its service life. In this work, the dadda multiplier is designed using the traditional energy-saving adder with cmos technology. The dadda multiplier has become the most popular tree multiplier due to its high computational speed and low hardware configuration. Most of the delay of the dadda multiplier depends on the partial and final sum of the product. Energy-saving full adders and half adders are used to reduce the total power requirement of the dadda multiplier. The dadda multiplier uses modified adder design and is compared to traditional cmos adder. The two designs are computed by using with and without partitioning the technique. The power and delay of each dadda multiplier are analyzed using the Tanner EDA tool. The analysis of the expected results shows that the partitioned multiplier with conventional and modified full adder logic works better than the unpartitioned multiplier with conventional and modified full adder.