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ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis最新文献

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Universal Application of Load Board (L/B) and Socket with Direct Current Tester (DCT) for Various Packages 通用应用负载板(L/B)和插座与直流测试仪(DCT)的各种封装
ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021p0330
Yi-Sheng Lin, Yu-Hsiang Hsiao, Pei-Yu Tseng, Yu-Jen Chang, Cheng-Hsin Liu, Yu-Ting Lin
{"title":"Universal Application of Load Board (L/B) and Socket with Direct Current Tester (DCT) for Various Packages","authors":"Yi-Sheng Lin, Yu-Hsiang Hsiao, Pei-Yu Tseng, Yu-Jen Chang, Cheng-Hsin Liu, Yu-Ting Lin","doi":"10.31399/asm.cp.istfa2021p0330","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0330","url":null,"abstract":"\u0000 We develop a new workflow with O/S tester (Direct Current Tester, DCT) to detect quickly the defect location of failure packages, which can be used in the semiconductor industry for E-FA (Electrical Failure Analysis) fault localization for short, leakage, and open defects. This paper introduces the capability and presents two case studies identifying the defect location of solder balls where DCT with defect mapping function is useful as a non-destructive analysis technique. In this paper, the new methodology and application of DCT on open and short defects in various packages with different sizes have been presented. The experimental results of the design testing program and an intender tooling were verified for the accuracy of the defect mapping function in determining the pin location to defect.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130457791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast and Effective Sample Preparation Technique for Backside Fault Isolation on GaN Packaged Devices GaN封装器件背面故障隔离快速有效的样品制备技术
ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021p0279
T. Colpaert, S. Verleye
{"title":"Fast and Effective Sample Preparation Technique for Backside Fault Isolation on GaN Packaged Devices","authors":"T. Colpaert, S. Verleye","doi":"10.31399/asm.cp.istfa2021p0279","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0279","url":null,"abstract":"\u0000 This paper describes a fast and effective sample preparation method to allow backside fault localization on GaN package devices. Backside analysis by Photon Emission Microscopy (PEM) is becoming preferable to frontside analysis when the die is covered by metal layers. This paper describes an optimized method for backside sample preparation on GaN package devices having a thick heavily doped p-type silicon substrate. The method combines mechanical and chemical deprocessing steps, resulting in a fast and effective sample preparation technique for PEM analysis. Additionally, the laser marking process parameters to facilitate orientation during the final physical failure analysis by Focused Ion Beam (FIB) are also shared.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"363 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115967138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Recent Developments for the Characterization of Crystals and Defects at the Nanoscale using On-Axis TKD in SEM 扫描电镜上轴TKD表征纳米尺度晶体和缺陷的最新进展
ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021p0217
D. Goran, T. Schwager, A. Fanta
{"title":"Recent Developments for the Characterization of Crystals and Defects at the Nanoscale using On-Axis TKD in SEM","authors":"D. Goran, T. Schwager, A. Fanta","doi":"10.31399/asm.cp.istfa2021p0217","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0217","url":null,"abstract":"\u0000 The development of advanced nanomaterials and nanodevices is dependent on the availability of powerful and reliable characterization techniques. In this context, we developed hardware and software capabilities to help push the spatial resolution limit during orientation mapping in a Scanning Electron Microscope (SEM).","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122550209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Credits 学分
ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021fm01
{"title":"Credits","authors":"","doi":"10.31399/asm.cp.istfa2021fm01","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021fm01","url":null,"abstract":"\u0000 Listings of the EDFAS 2021-2022 Board of Directors and ITSTFA 2021 Organizing Committee and Session Chairs.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134119163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Automated Metrology on the Verticality of Cross-Sectioned Channel Hole at V-NAND with Over 200 Layers by Transmission Electron Microscope 200层以上v型nand横截面孔洞垂直度的透射电镜自动测量
ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021p0313
Dong-yeob Kim, Jong-ick Son, C. H. Kang
{"title":"Automated Metrology on the Verticality of Cross-Sectioned Channel Hole at V-NAND with Over 200 Layers by Transmission Electron Microscope","authors":"Dong-yeob Kim, Jong-ick Son, C. H. Kang","doi":"10.31399/asm.cp.istfa2021p0313","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0313","url":null,"abstract":"\u0000 In this paper, we present a nanoscale verticality measurement method for V-NAND with 200 or more layers of high layers using an automated transmission electron microscope, which has been developed a lot in the analysis field. Nanoscale measurements in cross-sectional images in 3D-NAND with such a high layer do not include both the top and bottom areas in one image of FOV. Therefore, it is very difficult for a person to objectively measure the etching angle or verticality of the channel hole. We experimented the verticality measurement of a channel hole in the two images in different areas using an automated transmission electron microscope imaging and measurement. In this paper, we present the results and analysis of the experiment and detailed metrology methods.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115190165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pulsing Test for Defect of Resistive Word Line in DRAM Main Cell using WGFMU (Waveform Generator Fast Measurement Unit) 用WGFMU(波形发生器快速测量单元)脉冲检测DRAM主单元电阻字线缺陷
ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021p0258
Jaeyun Lee, EuiSeok Kim, JunYeal Lim, SeokHoon Oh, YoungHa Park
{"title":"Pulsing Test for Defect of Resistive Word Line in DRAM Main Cell using WGFMU (Waveform Generator Fast Measurement Unit)","authors":"Jaeyun Lee, EuiSeok Kim, JunYeal Lim, SeokHoon Oh, YoungHa Park","doi":"10.31399/asm.cp.istfa2021p0258","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0258","url":null,"abstract":"\u0000 In this paper, we compare and describe the difference between the oscilloscope pulsing test and the WGFMU (Waveform Generator Fast Measurement Unit) in analyzing the defect of high resistance in DRAM main cell sample. The nanoprobe system has many constraints in the pulsing analysis utilizing the oscilloscope and pulse generator. There are certain cases where the system cannot support analysis when the saturation current is extremely minimal, such as the DRAM cell. In this paper, we address this constraint and propose a new way to conduct pulsing tests using the WGFMU's arbitrary linear waveform generator in the nanoprobe system.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116133309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Demystifying Unexpected Silicon Responses through User-Defined Fault Models (UDFM) and Failure Analysis 通过用户自定义故障模型(UDFM)和故障分析揭开意外硅响应的神秘面纱
ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021p0369
Subhadip Kundu, Gaurav Bhargava, L. Endrinal, Lavakumar Ranganathan
{"title":"Demystifying Unexpected Silicon Responses through User-Defined Fault Models (UDFM) and Failure Analysis","authors":"Subhadip Kundu, Gaurav Bhargava, L. Endrinal, Lavakumar Ranganathan","doi":"10.31399/asm.cp.istfa2021p0369","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0369","url":null,"abstract":"\u0000 Failure Analysis (FA) plays an important role during silicon development and yield ramp up, helping identify critical test, design marginality and process issues in a timely and efficient manner. FA techniques typically rely on diagnosis callouts as a starting point for debug. Diagnostic algorithms rely on the error logs collected on production patterns which are generated to detect Stuck-at Faults (SAF) and Transition Delay Faults (TDF). Typically, SAF patterns screen out the static defects and TDF patterns test for transient fails. But often, we see cases where a SAF pattern shmoo is clean but the TDF pattern shmoo is a gross failure indicating a cell-internal static defect missed by the traditional SAF patterns. In this work, we will present our own developed User-Defined Fault Model, which targets cell-internal faults to explain unexpected silicon observations. An added advantage of the work can be seen in improving diagnosis results on the error logs collected using these targeted UDFM patterns. Since UDFM utilizes targeted fault excitation, the diagnosis algorithm results in better callouts. In this paper, we will also propose a custom diagnosis flow using our in-house UDFM to achieve better resolution. Three FA case studies will be presented to showcase the usefulness and effectivity of the proposed methods.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124893434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impacts of Substrate Thinning on FPGA Performance and Reliability 衬底薄化对FPGA性能和可靠性的影响
ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021p0423
D. Leonhardt, T. Beechem, M. Cannon, N. Dodds, Matthew Fellows, T. Grzybowski, G. Haase, Thomas LeBoeuf, David Lee, William Rice
{"title":"Impacts of Substrate Thinning on FPGA Performance and Reliability","authors":"D. Leonhardt, T. Beechem, M. Cannon, N. Dodds, Matthew Fellows, T. Grzybowski, G. Haase, Thomas LeBoeuf, David Lee, William Rice","doi":"10.31399/asm.cp.istfa2021p0423","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0423","url":null,"abstract":"\u0000 Global thinning of integrated circuits is a technique that enables backside failure analysis and radiation testing. Prior work also shows increased thresholds for single-event latchup and upset in thinned devices. We present impacts of global thinning on device performance and reliability of 28 nm node field programmable gate arrays (FPGA). Devices are thinned to values of 50, 10, and 3 microns using a micromachining and polishing method. Lattice damage, in the form of dislocations, extend about 1 micron below the machined surface. The damage layer is removed after polishing with colloidal SiO2 slurry. We create a 2D finite-element model with liner elasticity equations and flip-chip packaged device geometry to show that thinning increases compressive global stress in the Si, while C4 bumps increase stress locally. Measurements of stress using Raman spectroscopy qualitatively agree with our stress model but also reveal the need for more complex structural models to account for nonlinear effects occurring in devices thinned to 3 microns and after temperature cycling to 125°C. Thermal imaging shows that increased local heating occurs with increased thinning but the maximum temperature difference across the 3-micron die is less than 2°C. Ring oscillators (ROs) programmed throughout the FPGA fabric slow about 0.5% after thinning compared to full thickness values. Temperature cycling the devices to 125°C further decreases RO frequency about 0.5%, which we attribute to stress changes in the Si.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124945791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Selective Dry Etch Removal of Si and SiOxNy for Advanced Electron Beam Probing Applications 选择性干蚀刻去除先进电子束探测应用的Si和SiOxNy
ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021p0414
M. Edmonds, Thaddeus J. Cox, John Markulin, M. von Haartman
{"title":"Selective Dry Etch Removal of Si and SiOxNy for Advanced Electron Beam Probing Applications","authors":"M. Edmonds, Thaddeus J. Cox, John Markulin, M. von Haartman","doi":"10.31399/asm.cp.istfa2021p0414","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0414","url":null,"abstract":"\u0000 This paper presents a global die level sample preparation technique utilizing selective etch chemistry and laser interferometry to expose the entire die top-most metal layer surface for Ebeam electrical FI. A novel Ebeam based probing technique referred to as StaMPS is introduced alongside this prep technique to isolate logic structure failures observed through SEM image contrasts at different logic states. By landing SEM probe tips on exposed metal pads and controlling logic states via an applied bias, the varying states produce different contrast within SEM imaging highlighting structural failure locations. This global prep technique in combination with StaMPS Ebeam FI creates faster FI/FA turn-around time by delivering a globally delayered full die in under an hour and creating opportunity to locate several defect types within a single sample.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123048104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Failure Localization Techniques for 7nm & 16nm Process Nodes in Monolithic & 2.5D SSIT Package Technology Using OBIRCH, LVP and Advance Die Thinning Method 基于OBIRCH、LVP和Advance Die细化方法的单片和2.5D SSIT封装技术中7nm和16nm工艺节点失效定位技术
ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021p0073
D. Nuez, Phoumra Tan, Daisy Lu, B. Zhang, Joshua Miller, Mark Lynaugh, Thomas Harper, M. DiBattista, S. Silverman
{"title":"Failure Localization Techniques for 7nm & 16nm Process Nodes in Monolithic & 2.5D SSIT Package Technology Using OBIRCH, LVP and Advance Die Thinning Method","authors":"D. Nuez, Phoumra Tan, Daisy Lu, B. Zhang, Joshua Miller, Mark Lynaugh, Thomas Harper, M. DiBattista, S. Silverman","doi":"10.31399/asm.cp.istfa2021p0073","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0073","url":null,"abstract":"\u0000 High performance IC's have driven the semiconductor industry towards the sub-nanometer technology nodes for several years. At 16nm and beyond, the spatial resolution and sensitivity of some diagnostic equipment used for failure analysis have reached certain limitations. The accuracy of isolating a faulty signal in a tightly packed group of transistors in a die becomes more challenging. However, with the improvement of SIL (Solid Immersion Lens) based lens technology with higher N.A. (Numeric Aperture), combined with precision die thinning process, allowed some very promising results. This paper demonstrates successful diagnostic techniques utilizing the SIL lens and a variety of die thinning preparation techniques on 7nm and 16nm process nodes in both monolithic and 2.5D SSIT (Stacked Silicon Interconnect Technology) packages.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130060728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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