ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis最新文献_第2页

Universal Application of Load Board (L/B) and Socket with Direct Current Tester (DCT) for Various Packages 通用应用负载板(L/B)和插座与直流测试仪(DCT)的各种封装

ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021p0330

Yi-Sheng Lin, Yu-Hsiang Hsiao, Pei-Yu Tseng, Yu-Jen Chang, Cheng-Hsin Liu, Yu-Ting Lin

引用次数: 0

Fast and Effective Sample Preparation Technique for Backside Fault Isolation on GaN Packaged Devices GaN封装器件背面故障隔离快速有效的样品制备技术

ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021p0279

T. Colpaert, S. Verleye

引用次数: 0

Recent Developments for the Characterization of Crystals and Defects at the Nanoscale using On-Axis TKD in SEM 扫描电镜上轴TKD表征纳米尺度晶体和缺陷的最新进展

ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021p0217

D. Goran, T. Schwager, A. Fanta

引用次数: 0

Credits 学分

ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021fm01

引用次数: 0

Demystifying Unexpected Silicon Responses through User-Defined Fault Models (UDFM) and Failure Analysis 通过用户自定义故障模型(UDFM)和故障分析揭开意外硅响应的神秘面纱

ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021p0369

Subhadip Kundu, Gaurav Bhargava, L. Endrinal, Lavakumar Ranganathan

{"title":"Demystifying Unexpected Silicon Responses through User-Defined Fault Models (UDFM) and Failure Analysis","authors":"Subhadip Kundu, Gaurav Bhargava, L. Endrinal, Lavakumar Ranganathan","doi":"10.31399/asm.cp.istfa2021p0369","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0369","url":null,"abstract":"\u0000 Failure Analysis (FA) plays an important role during silicon development and yield ramp up, helping identify critical test, design marginality and process issues in a timely and efficient manner. FA techniques typically rely on diagnosis callouts as a starting point for debug. Diagnostic algorithms rely on the error logs collected on production patterns which are generated to detect Stuck-at Faults (SAF) and Transition Delay Faults (TDF). Typically, SAF patterns screen out the static defects and TDF patterns test for transient fails. But often, we see cases where a SAF pattern shmoo is clean but the TDF pattern shmoo is a gross failure indicating a cell-internal static defect missed by the traditional SAF patterns. In this work, we will present our own developed User-Defined Fault Model, which targets cell-internal faults to explain unexpected silicon observations. An added advantage of the work can be seen in improving diagnosis results on the error logs collected using these targeted UDFM patterns. Since UDFM utilizes targeted fault excitation, the diagnosis algorithm results in better callouts. In this paper, we will also propose a custom diagnosis flow using our in-house UDFM to achieve better resolution. Three FA case studies will be presented to showcase the usefulness and effectivity of the proposed methods.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124893434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Pulsing Test for Defect of Resistive Word Line in DRAM Main Cell using WGFMU (Waveform Generator Fast Measurement Unit) 用WGFMU(波形发生器快速测量单元)脉冲检测DRAM主单元电阻字线缺陷

ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021p0258

Jaeyun Lee, EuiSeok Kim, JunYeal Lim, SeokHoon Oh, YoungHa Park

引用次数: 0

Automated Metrology on the Verticality of Cross-Sectioned Channel Hole at V-NAND with Over 200 Layers by Transmission Electron Microscope 200层以上v型nand横截面孔洞垂直度的透射电镜自动测量

ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021p0313

Dong-yeob Kim, Jong-ick Son, C. H. Kang

引用次数: 0

Pushing Failure Mode Stimulus to Overcome the Limitation/Boundaries of Soft Defect Localization Tools 推失效模式刺激克服软缺陷定位工具的局限性/边界

ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021p0084

A. Norico, Rommel Estores

{"title":"Pushing Failure Mode Stimulus to Overcome the Limitation/Boundaries of Soft Defect Localization Tools","authors":"A. Norico, Rommel Estores","doi":"10.31399/asm.cp.istfa2021p0084","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0084","url":null,"abstract":"\u0000 Temperature dependent failures are some of the most challenging cases that will be encountered by the analyst. Soft Defect Localization (SDL) is a technique used to analyze such temperature-dependent, ‘soft defect’ failures [1]. There are many literatures that discuss this technique and its different applications [2-7]. Dynamic Analysis by Laser Stimulation (DALS) is one of the known SDL implementations [8-11]. However, there are cases where the failure is occurring at a temperature where the laser alone is not sufficient to effectively induce a change of device behavior. In these situations, the analyst needs to think out of the box by understanding how the device will react to external conditions and to make necessary adjustments in DALS settings. This paper will discuss three cases that presents different challenges such as performing DALS analysis where the failing temperature is too high for the laser to induce a change of behavior from ambient temperature, cold temperature failure, complex triggering (Serial Peripheral Interface, SPI), and using an internal signal as input for DALS analysis. The approach used for a successful DALS analysis of each case will be discussed in detail.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128771814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impacts of Substrate Thinning on FPGA Performance and Reliability 衬底薄化对FPGA性能和可靠性的影响

ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021p0423

D. Leonhardt, T. Beechem, M. Cannon, N. Dodds, Matthew Fellows, T. Grzybowski, G. Haase, Thomas LeBoeuf, David Lee, William Rice

{"title":"Impacts of Substrate Thinning on FPGA Performance and Reliability","authors":"D. Leonhardt, T. Beechem, M. Cannon, N. Dodds, Matthew Fellows, T. Grzybowski, G. Haase, Thomas LeBoeuf, David Lee, William Rice","doi":"10.31399/asm.cp.istfa2021p0423","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0423","url":null,"abstract":"\u0000 Global thinning of integrated circuits is a technique that enables backside failure analysis and radiation testing. Prior work also shows increased thresholds for single-event latchup and upset in thinned devices. We present impacts of global thinning on device performance and reliability of 28 nm node field programmable gate arrays (FPGA). Devices are thinned to values of 50, 10, and 3 microns using a micromachining and polishing method. Lattice damage, in the form of dislocations, extend about 1 micron below the machined surface. The damage layer is removed after polishing with colloidal SiO2 slurry. We create a 2D finite-element model with liner elasticity equations and flip-chip packaged device geometry to show that thinning increases compressive global stress in the Si, while C4 bumps increase stress locally. Measurements of stress using Raman spectroscopy qualitatively agree with our stress model but also reveal the need for more complex structural models to account for nonlinear effects occurring in devices thinned to 3 microns and after temperature cycling to 125°C. Thermal imaging shows that increased local heating occurs with increased thinning but the maximum temperature difference across the 3-micron die is less than 2°C. Ring oscillators (ROs) programmed throughout the FPGA fabric slow about 0.5% after thinning compared to full thickness values. Temperature cycling the devices to 125°C further decreases RO frequency about 0.5%, which we attribute to stress changes in the Si.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124945791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Wafer Pattern Recognition for Detecting Process Abnormalities in NAND Flash Memory Manufacturing 用于NAND快闪记忆体制造过程异常侦测的晶圆模式识别

ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI: 10.31399/asm.cp.istfa2021p0406

Jeongin Choe, Taehyeon Kim, Saetbyeol Yoon, Sangyong Yoon, Ki-Whan Song, J. Song, Myungsuk Kim, Woo Young Choi

引用次数: 0