Failure Localization Techniques for 7nm & 16nm Process Nodes in Monolithic & 2.5D SSIT Package Technology Using OBIRCH, LVP and Advance Die Thinning Method

ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis Pub Date : 2021-10-31 DOI:10.31399/asm.cp.istfa2021p0073

D. Nuez, Phoumra Tan, Daisy Lu, B. Zhang, Joshua Miller, Mark Lynaugh, Thomas Harper, M. DiBattista, S. Silverman

{"title":"Failure Localization Techniques for 7nm & 16nm Process Nodes in Monolithic & 2.5D SSIT Package Technology Using OBIRCH, LVP and Advance Die Thinning Method","authors":"D. Nuez, Phoumra Tan, Daisy Lu, B. Zhang, Joshua Miller, Mark Lynaugh, Thomas Harper, M. DiBattista, S. Silverman","doi":"10.31399/asm.cp.istfa2021p0073","DOIUrl":null,"url":null,"abstract":"\n High performance IC's have driven the semiconductor industry towards the sub-nanometer technology nodes for several years. At 16nm and beyond, the spatial resolution and sensitivity of some diagnostic equipment used for failure analysis have reached certain limitations. The accuracy of isolating a faulty signal in a tightly packed group of transistors in a die becomes more challenging. However, with the improvement of SIL (Solid Immersion Lens) based lens technology with higher N.A. (Numeric Aperture), combined with precision die thinning process, allowed some very promising results. This paper demonstrates successful diagnostic techniques utilizing the SIL lens and a variety of die thinning preparation techniques on 7nm and 16nm process nodes in both monolithic and 2.5D SSIT (Stacked Silicon Interconnect Technology) packages.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.31399/asm.cp.istfa2021p0073","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

Abstract

High performance IC's have driven the semiconductor industry towards the sub-nanometer technology nodes for several years. At 16nm and beyond, the spatial resolution and sensitivity of some diagnostic equipment used for failure analysis have reached certain limitations. The accuracy of isolating a faulty signal in a tightly packed group of transistors in a die becomes more challenging. However, with the improvement of SIL (Solid Immersion Lens) based lens technology with higher N.A. (Numeric Aperture), combined with precision die thinning process, allowed some very promising results. This paper demonstrates successful diagnostic techniques utilizing the SIL lens and a variety of die thinning preparation techniques on 7nm and 16nm process nodes in both monolithic and 2.5D SSIT (Stacked Silicon Interconnect Technology) packages.

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基于OBIRCH、LVP和Advance Die细化方法的单片和2.5D SSIT封装技术中7nm和16nm工艺节点失效定位技术

近年来，高性能集成电路推动半导体产业向亚纳米技术节点发展。在16nm及以上，一些用于故障分析的诊断设备的空间分辨率和灵敏度已经达到一定的极限。在芯片中紧密排列的一组晶体管中隔离错误信号的准确性变得更具挑战性。然而，随着基于SIL(固体浸没透镜)的透镜技术的改进，具有更高的N.A.(数值孔径)，结合精确的模具细化工艺，允许一些非常有希望的结果。本文展示了在单片和2.5D SSIT(堆叠硅互连技术)封装中利用SIL透镜和各种7nm和16nm工艺节点上的芯片减薄制备技术的成功诊断技术。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis

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