1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)最新文献_第10页

Global Harmony: coupled noise analysis for full-chip RC interconnect networks 全球和谐:全芯片RC互连网络的耦合噪声分析

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643396

K. Shepard, V. Narayanan, P. C. Elmendorf, Gutuan Zheng

引用次数: 88

Hierarchical partitioning for field-programmable systems 现场可编程系统的分层划分

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643571

V. Chan, D. Lewis

引用次数: 2

An efficient statistical analysis methodology and its application to high-density DRAMs 一种高效的统计分析方法及其在高密度dram中的应用

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643611

Sang-Hoon Lee, Chang-hoon Choi, J. Kong, Wong-Seong Lee, Jei-Hwan Yoo

引用次数: 16

A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists 一个基于sat的隐含引擎，用于高效的ATPG，等价性检查和网络列表的优化

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643607

P. Tafertshofer, A. Ganz, M. Henftling

引用次数: 70

Optimal wire and transistor sizing for circuits with non-tree topology 非树形拓扑电路的最佳导线和晶体管尺寸

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643528

L. Vandenberghe, Stephen P. Boyd, A. Gamal

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引用次数: 37

Delay bounded buffered tree construction for timing driven floorplanning 延迟有界缓冲树形结构用于定时驱动的楼层规划

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643616

M. Kang, W. Dai, Tom Dillinger, D. LaPotin

引用次数: 23

Logic synthesis for large pass transistor circuits 大通路晶体管电路的逻辑合成

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643609

Premal Buch, A. Narayan, A. Newton, A. Sangiovanni-Vincentelli

{"title":"Logic synthesis for large pass transistor circuits","authors":"Premal Buch, A. Narayan, A. Newton, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1997.643609","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643609","url":null,"abstract":"Pass transistor logic (PTL) can be a promising alternative to static CMOS for deep sub-micron design. The authors motivate the need for CAD algorithms for PTL circuit design and propose decomposed BDDs as a suitable logic level representation for synthesis of PTL networks. Decomposed BDDs can represent large, arbitrary functions as a multistage circuit and can exploit the natural, efficient mapping of a BDD to PTL. A comprehensive synthesis flow based on decomposed BDDs is outlined for PTL design. They show that the proposed approach allows one to make logic-level optimizations similar to the traditional multi-level network based synthesis flow for static CMOS, and also makes possible optimizations with a direct impact on area, delay and power of the final circuit implementation which do nor have any equivalent in the traditional approach. They also present a set of heuristical algorithms to synthesize PTL circuits optimized for area, delay and power which are key to the proposed synthesis flow. Experimental results on ISCAS benchmark circuits show that the technique yields PTL circuits with substantial improvements over static CMOS designs. In addition, to the best of their knowledge this is the first time PTL circuits have been synthesized for the entire ISCAS benchmark set.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115307755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 124

Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systems 微抢占综合:多任务VLSI系统的使能机制

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1900-01-01 DOI: 10.1109/iccad.1997.643272

Kyosun Kim, R. Karri, M. Potkonjak

引用次数: 2

Global interconnect sizing and spacing with consideration of coupling capacitance 考虑耦合电容的全局互连尺寸和间距

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1900-01-01 DOI: 10.1109/iccad.1997.643604

J. Cong, Lei He, Cheng-Kok Koh, D. Pan

引用次数: 39