1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)最新文献

Effects of delay models on peak power estimation of VLSI sequential circuits 延迟模型对VLSI顺序电路峰值功率估计的影响

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643360

M. Hsiao, E. Rudnick, J. Patel

引用次数: 42

Hardware/software partitioning for multi-function systems 用于多功能系统的硬件/软件分区

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643588

A. Kalavade, 07733. subra

{"title":"Hardware/software partitioning for multi-function systems","authors":"A. Kalavade, 07733. subra","doi":"10.1109/ICCAD.1997.643588","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643588","url":null,"abstract":"We are interested in optimizing the design of multi-function embedded systems that run a pre-specified set of applications, such as multi-standard audio/video codecs and multi-system phones. Such systems usually have stringent performance constraints and tend to have mixed hardware-software implementations. The current stare of the art in the hardware/software codesign of such systems is to design for each application separately. This often leads to application-specific sub-optimal decisions and inconsistent mappings of common nodes in different applications. We use these as the guiding principles to formulate, as a codesign problem, the design and synthesis of an efficient hardware-software implementation for a multi-function embedded system. Our solution methodology is to first identify nodes that represent similar functionality across different applications. Such \"common\" nodes are characterized by several metrics. These metrics are quantified and used by a hardware/software partitioning tool to map common nodes to the same resource as far as possible. We demonstrate how this is achieved by modifying a traditional partitioning algorithm (GCLP) used to partition single applications. The overall result of the system-level partitioning process is (1) a hardware or software mapping and (2) a schedule for execution for each node within the application set. On an example set consisting of three video applications, we show that the solution obtained by the use of our method is 38% smaller than that obtained when each application is considered independently.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126908302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 41

State transformation in event driven explicit simulation 事件驱动显式仿真中的状态转换

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643533

Tuyen V. Nguyen, A. Devgan

引用次数: 0

Post-route optimization for improved yield using a rubber-band wiring model 利用橡皮筋布线模型进行产率优化

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643615

Jeffrey Z. Su, W. Dai

引用次数: 22

A quantitative approach to functional debugging 功能调试的定量方法

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643403

D. Kirovski, M. Potkonjak

引用次数: 6

A block rational Arnoldi algorithm for multipoint passive model-order reduction of multiport RLC networks 多端口RLC网络多点被动模型降阶的块理性Arnoldi算法

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643368

I. Elfadel, D. D. Ling

{"title":"A block rational Arnoldi algorithm for multipoint passive model-order reduction of multiport RLC networks","authors":"I. Elfadel, D. D. Ling","doi":"10.1109/ICCAD.1997.643368","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643368","url":null,"abstract":"Work in the area of model-order reduction for RLC interconnect networks has focused on building reduced-order models that preserve the circuit-theoretic properties of the network, such as stability, passivity, and synthesizability (Silveira et al., 1996). Passivity is the one circuit-theoretic property that is vital for the successful simulation of a large circuit netlist containing reduced-order models of its interconnect networks. Non-passive reduced-order models may lead to instabilities even if they are themselves stable. We address the problem of guaranteeing the accuracy and passivity of reduced-order models of multiport RLC networks at any finite number of expansion points. The novel passivity-preserving model-order reduction scheme is a block version of the rational Arnoldi algorithm (Ruhe, 1994). The scheme reduces to that of (Odabasioglu et al., 1997) when applied to a single expansion point at zero frequency. Although the treatment of this paper is restricted to expansion points that are on the negative real axis, it is shown that the resulting passive reduced-order model is superior in accuracy to the one that would result from expanding the original model around a single point. Nyquist plots are used to illustrate both the passivity and the accuracy of the reduced order models.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"50 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124528501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 160

Interconnect layout optimization under higher-order RLC model 高阶RLC模型下互连布局优化

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643617

J. Cong, Cheng-Kok Koh

引用次数: 38

The disjunctive decomposition of logic functions 逻辑函数的析取分解

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643371

V. Bertacco, M. Damiani

引用次数: 132

Fast field solver programs for thermal and electrostatic analysis of microsystem elements 用于微系统元素的热和静电分析的快速场求解程序

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643612

V. Székely, M. Rencz

引用次数: 7

Simulated quenching: a new placement method for module generation 模拟淬火:一种新的模块生成放置方法

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1997-11-13 DOI: 10.1109/ICCAD.1997.643591

Shinji Sato

引用次数: 9