Global interconnect sizing and spacing with consideration of coupling capacitance

J. Cong, Lei He, Cheng-Kok Koh, D. Pan
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引用次数: 39

Abstract

The paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of coupling capacitance, in addition to area and fringing capacitances. We introduce the formulation of symmetric and asymmetric wire sizing and spacing. We prove two important results on the symmetric and asymmetric effective fringing properties which lead to a very effective bound computation algorithm to compute the upper and lower bounds of the optimal wire sizing and spacing solution for all nets under consideration. Our experiments show that in most cases the upper and lower bounds meet quickly after a few iterations and we actually obtain the optimal solution. To our knowledge, this is the first in depth study of global wire sizing and spacing for multiple nets with consideration of coupling capacitance. Experimental results show that our GISS solutions lead to substantially better delay reduction than existing single net wire sizing solutions without consideration of coupling capacitance.
考虑耦合电容的全局互连尺寸和间距
本文提出了一种有效的方法对多个网络进行全局互连尺寸和间距(GISS),以最小化互连延迟,同时考虑耦合电容,以及面积和边缘电容。我们介绍了对称和非对称线材尺寸和间距的公式。我们证明了对称和非对称有效边化性质的两个重要结果,从而得出了一种非常有效的边界计算算法,可以计算所有考虑的网的最优线径和间距解的上界和下界。我们的实验表明,在大多数情况下,经过几次迭代,上界和下界很快就会满足,我们实际上得到了最优解。据我们所知,这是第一次在考虑耦合电容的情况下对多个网络的整体线径和间距进行深入研究。实验结果表明,我们的GISS解决方案比现有的不考虑耦合电容的单网线尺寸解决方案具有更好的延迟降低效果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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