2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第4页

High-Level Synthesis of Transactional Memory 事务性内存的高级综合

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431556

Omar Ragheb, J. Anderson

{"title":"High-Level Synthesis of Transactional Memory","authors":"Omar Ragheb, J. Anderson","doi":"10.1145/3394885.3431556","DOIUrl":"https://doi.org/10.1145/3394885.3431556","url":null,"abstract":"The rising popularity of high-level synthesis (HLS) is due to the complexity and amount of background knowledge required to design hardware circuits. Despite significant recent advances in HLS research, HLS-generated circuits may be of lower quality than human-expert-designed circuits, from the performance, power, or area perspectives. In this work, we aim to raise circuit performance by introducing a transactional memory (TM) synchronization model to the open-source LegUp HLS tool [1]. LegUp HLS supports the synthesis of multi-threaded software into parallel hardware [4], including support for mutual-exclusion lock-based synchronization. With the introduction of transactional memory-based synchronization, location-specific (i.e. finer grained) memory locks are made possible, where instead of placing an access lock around an entire array, one can place a lock around individual array elements. Significant circuit performance improvements are observed through reduced stalls due to contention, and greater memory-access parallelism. On a set of 5 parallel benchmarks, wall-clock time is improved by 2.0×, on average, by the TM synchronization model vs. mutex-based locks.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116363676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A DSM-based Polar Transmitter with 23.8% System Efficiency 基于dsm的极态发射机，系统效率为23.8%

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431653

Yuncheng Zhang, Bangan Liu, Xiaofan Gu, Chun Wang, A. Shirane, K. Okada

引用次数: 0

Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models 基于机器学习模型的模拟布局快速有效约束评估

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431547

Tonmoy Dhar, Jitesh Poojary, Yaguang Li, K. Kunal, Meghna Madhusudan, A. Sharma, Susmita Dey Manasi, Jiang Hu, R. Harjani, S. Sapatnekar

引用次数: 6

Efficient Computing Platform Design for Autonomous Driving Systems 自动驾驶系统高效计算平台设计

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431620

Shuang Liang, Changcheng Tang, Xuefei Ning, Shulin Zeng, Jincheng Yu, Yu Wang, Kaiyuan Guo, Diange Yang, Tianyi Lu, Huazhong Yang

{"title":"Efficient Computing Platform Design for Autonomous Driving Systems","authors":"Shuang Liang, Changcheng Tang, Xuefei Ning, Shulin Zeng, Jincheng Yu, Yu Wang, Kaiyuan Guo, Diange Yang, Tianyi Lu, Huazhong Yang","doi":"10.1145/3394885.3431620","DOIUrl":"https://doi.org/10.1145/3394885.3431620","url":null,"abstract":"Autonomous driving is becoming a hot topic in both academic and industrial communities. Traditional algorithms can hardly achieve the complex tasks and meet the high safety criteria. Recent research on deep learning shows significant performance improvement over traditional algorithms and is believed to be a strong candidate in autonomous driving system. Despite the attractive performance, deep learning does not solve the problem totally. The application scenario requires that an autonomous driving system must work in real-time to keep safety. But the high computation complexity of neural network model, together with complicated pre-process and post-process, brings great challenges. System designers need to do dedicated optimizations to make a practical computing platform for autonomous driving. In this paper, we introduce our work on efficient computing platform design for autonomous driving systems. In the software level, we introduce neural network compression and hardware-aware architecture search to reduce the workload. In the hardware level, we propose customized hardware accelerators for pre- and post-process of deep learning algorithms. Finally, we introduce the hardware platform design, NOVA-30, and our on-vehicle evaluation project.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124811607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment 多fpga协同优化:混合路由和基于竞争的时分复用分配

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431565

Dan Zheng, Xiaopeng Zhang, Chak-Wa Pui, Evangeline F. Y. Young

{"title":"Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment","authors":"Dan Zheng, Xiaopeng Zhang, Chak-Wa Pui, Evangeline F. Y. Young","doi":"10.1145/3394885.3431565","DOIUrl":"https://doi.org/10.1145/3394885.3431565","url":null,"abstract":"In multi-FPGA systems, time-division multiplexing (TDM) is a widely used technique to transfer signals between FPGAs. While TDM can greatly increase logic utilization, the inter-FPGA delay will also become longer. A good time-multiplexing scheme for inter-FPGA signals is very important for optimizing the system performance. In this work, we propose a fast algorithm to generate high quality time-multiplexed routing results for multiple FPGA systems. A hybrid routing algorithm is proposed to route the nets between FPGAs, by maze routing and by a fast minimum terminal spanning tree method. After obtaining a routing topology, a two-step method is applied to perform TDM assignment to optimize timing, which includes an initial assignment and a competitive-based refinement. Experiments show that our system-level routing and TDM assignment algorithm can outperform both the top winner of the ICCAD 2019 Contest and the state-of-the-art methods. Moreover, compared to the state-of-the-art works [17], [22], our approach has better run time by more than 2X with better or comparable TDM performance.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129641124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Multi-Commodity Network Flow Based Routing Algorithm for Paper-Based Digital Microfluidic Biochips 基于多商品网络流的纸质数字微流控生物芯片路由算法

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431611

Nai-Ren Shih, Tsung-Yi Ho

{"title":"A Multi-Commodity Network Flow Based Routing Algorithm for Paper-Based Digital Microfluidic Biochips","authors":"Nai-Ren Shih, Tsung-Yi Ho","doi":"10.1145/3394885.3431611","DOIUrl":"https://doi.org/10.1145/3394885.3431611","url":null,"abstract":"Paper-based digital microfluidic biochips (P-DMFBs) have emerged as a safe, low-cost, and fast-responsive platform for biochemical assays. In P-DMFB, droplet manipulations are executed by the electrowetting technology. In order to enable the electrowetting technology, pattern arrays of electrodes and control lines are coated on paper with a hydrophobic Teflon film and dielectric parylene-C film. Different from traditional DMFBs, the manufacturing of P-DMFBs is efficient and inexpensive since the electrodes and control lines are printed on photo paper with an inkjet printer. Active paperbased hybridized chip (APHC) is a type of P-DMFBs that has open and closed part. APHC enjoys more convenience than common P-DMFBs since it has no need to fabricate and maintain the micro gap between glass and paper chip, which requires highly delicate treatments. However, the pattern rails of electrodes in APHCs are denser than traditional P-DMFBs, which makes existing electrode routing algorithm fail in APHCs. To deal with the challenge in electrode routing of APHCs, this paper proposes a multi-commodity network flow-based routing algorithm, which simultaneously maximizes the routability and minimizes the total wire length of control lines. The multi-commodity flow model can utilize the pin-sharing between electrodes, which can improve routability and reduce the detour of routing lines. Moreover, the activation sequences of electrodes are considered, which guarantees that the bioassay will not be interfered with after pin-sharing. The proposed method achieves a 100% successful routing rate on real-life APHCs while other electrode routing method cannot solve the electrode routing of APHCs successfully.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127138206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Physical-Aware Framework for Memory Network Design Space Exploration 存储网络设计空间探索的物理感知框架

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431636

Tianhao Shen, Di Gao, Li Zhang, Jishen Zhao, Cheng Zhuo

引用次数: 0

Efficient Techniques for Training the Memristor-based Spiking Neural Networks Targeting Better Speed, Energy and Lifetime 以更快的速度、能量和寿命为目标训练基于记忆电阻的脉冲神经网络的有效技术

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431555

Yu Ma, Pingqiang Zhou

引用次数: 1

A 0.57-GOPS/DSP Object Detection PIM Accelerator on FPGA 基于FPGA的0.57-GOPS/DSP目标检测PIM加速器

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431659

Bo Jiao, Jinshan Zhang, Yu-Jin Xie, Shunli Wang, Haozhe Zhu, Xiaoyang Kang, Zhiyan Dong, Lihua Zhang, Chixiao Chen

引用次数: 7

Machine Learning-based Structural Pre-route Insertability Prediction and Improvement with Guided Backpropagation* 基于机器学习的结构预路由可插入性预测与改进*

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431564

Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Chin-Hsiung Hsu, P. H. Tai, Cindy Chin-Fang Shen

{"title":"Machine Learning-based Structural Pre-route Insertability Prediction and Improvement with Guided Backpropagation*","authors":"Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Chin-Hsiung Hsu, P. H. Tai, Cindy Chin-Fang Shen","doi":"10.1145/3394885.3431564","DOIUrl":"https://doi.org/10.1145/3394885.3431564","url":null,"abstract":"With the development of semiconductor technology nodes, the sizes of standard cells become smaller and the number of standard cells is dramatically increased to bring into more functionality in integrated circuits (ICs). However, the shrinking of standard cell sizes causes many problems of ICs such as timing, power, and electromigration (EM). To tackle these problems, a new style structural pre-route (SPR) is proposed. Such type of pre-route is composed of redundant parallel metals and vias so that the low resistance and the redundant sub-structures can improve timing and yield. But the large area overhead becomes the major problem of inserting such pre-routes all over a design. In this paper, we propose a machine learning-based approach to predict the insertability of SPRs for placed designs. In addition, we apply a pattern visualization method by using a guided backpropagation technique to see in depth of our model and identify the problematic layout features causing SPR insertion failures. The experimental results not only show the excellent performance of our model, but also show that avoiding generating the identified critical features during legalization can improve SPR insertability compared to a commercial SPR-aware placement tool.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"121 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128492977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0