High-Level Synthesis of Transactional Memory

The rising popularity of high-level synthesis (HLS) is due to the complexity and amount of background knowledge required to design hardware circuits. Despite significant recent advances in HLS research, HLS-generated circuits may be of lower quality than human-expert-designed circuits, from the performance, power, or area perspectives. In this work, we aim to raise circuit performance by introducing a transactional memory (TM) synchronization model to the open-source LegUp HLS tool [1]. LegUp HLS supports the synthesis of multi-threaded software into parallel hardware [4], including support for mutual-exclusion lock-based synchronization. With the introduction of transactional memory-based synchronization, location-specific (i.e. finer grained) memory locks are made possible, where instead of placing an access lock around an entire array, one can place a lock around individual array elements. Significant circuit performance improvements are observed through reduced stalls due to contention, and greater memory-access parallelism. On a set of 5 parallel benchmarks, wall-clock time is improved by 2.0×, on average, by the TM synchronization model vs. mutex-based locks.