2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第5页

Learning Boolean Circuits from Examples for Approximate Logic Synthesis 从近似逻辑合成的例子中学习布尔电路

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431559

Sina Boroumand, C. Bouganis, G. Constantinides

{"title":"Learning Boolean Circuits from Examples for Approximate Logic Synthesis","authors":"Sina Boroumand, C. Bouganis, G. Constantinides","doi":"10.1145/3394885.3431559","DOIUrl":"https://doi.org/10.1145/3394885.3431559","url":null,"abstract":"Many computing applications are inherently error resilient. Thus, it is possible to decrease computing accuracy to achieve greater efficiency in area, performance, and/or energy consumption. In recent years, a slew of automatic techniques for approximate computing has been proposed; however, most of these techniques require full knowledge of an exact, or ‘golden’ circuit description. In contrast, there has been significant recent interest in synthesizing computation from examples, a form of supervised learning. In this paper, we explore the relationship between supervised learning of Boolean circuits and existing work on synthesizing incompletely-specified functions. We show that when considered through a machine learning lens, the latter work provides a good training accuracy but poor test accuracy. We contrast this with prior work from the 1990s which uses mutual information to steer the search process, aiming for good generalization. By combining this early work with a recent approach to learning logic functions, we are able to achieve a scalable and efficient machine learning approach for Boolean circuits in terms of area/delay/test-error trade-off.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117242307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

GRA-LPO: Graph Convolution Based Leakage Power Optimization GRA-LPO:基于图卷积的泄漏功率优化

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431574

U. Mallappa, Chung-Kuan Cheng

{"title":"GRA-LPO: Graph Convolution Based Leakage Power Optimization","authors":"U. Mallappa, Chung-Kuan Cheng","doi":"10.1145/3394885.3431574","DOIUrl":"https://doi.org/10.1145/3394885.3431574","url":null,"abstract":"Static power consumption is a critical challenge for IC designs, particularly for mobile and IoT applications. A final post-layout step in modern design flows involves a leakage recovery step that is embedded in signoff static timing analysis tools. The goal of such recovery is to make use of the positive slack (if any) and recover the leakage power by performing cell swaps with footprint compatible variants. Though such swaps result in unaltered routing, the hard constraint is not to introduce any new timing violations. This process can require up to tens of hours of runtime, just before the tapeout, when schedule and resource constraints are tightest. The physical design teams can benefit greatly from a fast predictor of the leakage recovery step: if the eventual recovery will be too small, the entire step can be skipped, and the resources can be allocated elsewhere. If we represent the circuit netlist as a graph with cells as vertices and nets connecting these cells as edges, the leakage recovery step is an optimization step, on this graph. If we can learn these optimizations over several graphs with various logic-cone structures, we can generalize the learning to unseen graphs. Using graph convolution neural networks, we develop a learning-based model, that predicts per-cell recoverable slack, and translate these slack values to equivalent power savings. For designs up to 1.6M instances, our inference step takes less than 12 seconds on a Tesla P100 GPU, and an additional feature extraction, post-processing steps consuming 420 seconds. The model is accurate with relative error under 6.2%, for the design-specific context.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125402630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Optimizing Temporal Decoupling using Event Relevance 使用事件相关性优化时间解耦

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431419

Lukas Jünger, Carmine Bianco, Kristof Niederholtmeyer, D. Petras, R. Leupers

{"title":"Optimizing Temporal Decoupling using Event Relevance","authors":"Lukas Jünger, Carmine Bianco, Kristof Niederholtmeyer, D. Petras, R. Leupers","doi":"10.1145/3394885.3431419","DOIUrl":"https://doi.org/10.1145/3394885.3431419","url":null,"abstract":"Over the last decades, HW/SW systems have grown ever more complex. System simulators, so called virtual platforms, have been an important tool for developing and testing these systems. However, the rise in overall complexity has also impacted the simulators. Complex platforms require fast simulation components and a sophisticated simulation infrastructure to meet today’s performance demands. With the introduction of SystemC TLM2.0, temporal decoupling has become a staple in the arsenal of simulation acceleration techniques. Temporal decoupling yields a significant simulation performance increase at the cost of diminished accuracy. The two prevalent approaches are called static quantum and dynamic quantum. In this work both are analyzed using a state-of-the-art, industrial virtual platform as a case study. While dynamic quantum offers an ideal trade-off between simulation performance and accuracy in a single-core scenario, performance reductions can be observed in multi-core platforms. To address this, a novel performance optimization is proposed, achieving a 14.32% performance gain in our case study while keeping near-perfect accuracy.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127512822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks 基于图神经网络的模拟电路布局对称标注

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431545

Xiaohan Gao, Chenhui Deng, Mingjie Liu, Zhiru Zhang, D. Pan, Yibo Lin

引用次数: 20

Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures MPMCT门到最近邻体系结构的动态分解和映射

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431605

A. Matsuo, Wakaki Hattori, S. Yamashita

引用次数: 1

A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization 基于局部惩罚的模拟电路合成鲁棒批贝叶斯优化

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431543

Jiangli Huang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng

{"title":"A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization","authors":"Jiangli Huang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng","doi":"10.1145/3394885.3431543","DOIUrl":"https://doi.org/10.1145/3394885.3431543","url":null,"abstract":"Bayesian optimization has been successfully introduced to analog circuit synthesis recently. Since the evaluations of performances are computational expensive, batch Bayesian optimization has been proposed to run simulations in parallel. However, circuit simulations may fail during the optimization, due to the improper design variables. In such cases, Bayesian optimization methods may have poor performance. In this paper, we propose a Robust Batch Bayesian Optimization approach (RBBO) for analog circuit synthesis. Local penalization (LP) is used to capture the local repulsion between query points in one batch. The diversity of the query points can thus be guaranteed. The failed points and their neighborhoods can also be excluded by LP. Moreover, we propose an Adaptive Local Penalization (ALP) strategy to adaptively scale the penalized areas to improve the convergence of our proposed RBBO method. The proposed approach is compared with the state-of-the-art algorithms with several practical analog circuits. The experimental results have demonstrated the efficiency and robustness of the proposed method.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121647074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Design Space Exploration of Heterogeneous-Accelerator SoCs with Hyperparameter Optimization 基于超参数优化的异构加速器soc设计空间探索

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431415

Thanh Cong, François Charot

{"title":"Design Space Exploration of Heterogeneous-Accelerator SoCs with Hyperparameter Optimization","authors":"Thanh Cong, François Charot","doi":"10.1145/3394885.3431415","DOIUrl":"https://doi.org/10.1145/3394885.3431415","url":null,"abstract":"Modern SoC systems consist of general-purpose processor cores augmented with large numbers of specialized accelerators. Building such systems requires a design flow allowing the design space to be explored at the system level with an appropriate strategy. In this paper, we describe a methodology allowing to explore the design space of power-performance heterogeneous SoCs by combining an architecture simulator (gem5-Aladdin) and a hyperparameter optimization method (Hyperopt). This methodology allows different types of parallelism with loop unrolling strategies and memory coherency interfaces to be swept. The flow has been applied to a convolutional neural network algorithm. We show that the most energy efficient architecture achieves a 2x to 4x improvement in energy-delay-product compared to an architecture without parallelism. Furthermore, the obtained solution is more efficient than commonly implemented architectures (Systolic, 2D-mapping, and Tiling). We also applied the methodology to find the optimal architecture including its coherency interface for a complex SoC made up of six accelerated-workloads. We show that a hybrid interface appears to be the most efficient; it reaches 22% and 12% improvement in energy-delay-product compared to just only using non-coherent and only LLC-coherent models, respectively.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122783835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A High Accuracy Phase and Amplitude Detection Circuit for Calibration of 28GHz Phased Array Beamformer System 一种用于28GHz相控阵波束形成系统标定的高精度相位和幅度检测电路

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431648

Joshua Alvin, Jian Pang, A. Shirane, K. Okada

引用次数: 1

Approximate Computing for ML: State-of-the-art, Challenges and Visions 机器学习的近似计算:现状、挑战和展望

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431632

Georgios Zervakis, Hassaan Saadat, H. Amrouch, A. Gerstlauer, S. Parameswaran, J. Henkel

引用次数: 21

ML-augmented Methodology for Fast Thermal Side-channel Emission Analysis 快速热侧通道发射分析的ml增强方法

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431641

N. Chang, Deqi Zhu, Lang Lin, D. Selvakumaran, Jimin Wen, S. Pan, W. Xia, Hua Chen, C. Chow, Gary Chen

{"title":"ML-augmented Methodology for Fast Thermal Side-channel Emission Analysis","authors":"N. Chang, Deqi Zhu, Lang Lin, D. Selvakumaran, Jimin Wen, S. Pan, W. Xia, Hua Chen, C. Chow, Gary Chen","doi":"10.1145/3394885.3431641","DOIUrl":"https://doi.org/10.1145/3394885.3431641","url":null,"abstract":"Accurate side-channel attacks can non-invasively or semi-invasively extract secure information from hardware devices using \"side- channel\" measurements. The thermal profile of an IC is one class of side channel that can be used to exploit the security weaknesses in a design. Measurement of junction temperature from an on-chip thermal sensor or top metal layer temperature using an infrared thermal image of an IC with the package being removed can disclose secret keys of a cryptographic design through correlation power analysis. In order to identify the design vulnerabilities to thermal side channel attacks, design time simulation tools are highly important. However, simulation of thermal side-channel emission is highly complex and computationally intensive due to the scale of simulation vectors required and the multi-physics simulation models involved. Hence, in this paper, we have proposed a fast and comprehensive Machine Learning (ML) augmented thermal simulation methodology for thermal Side-Channel emission Analysis (SCeA). We have developed an innovative tile-based Delta-T Predictor using a data-driven DNN-based thermal solver. The developed tile based Delta-T Predictor temperature is used to perform the thermal side-channel analysis which models the scenario of thermal attacks with the measurement of junction temperature. This method can be 100-1000x faster depending on the size of the chip compared to traditional FEM-based thermal solvers with the same level of accuracy. Furthermore, this simulation allows for the determination of location- dependent wire temperature on the top metal layer to validate the scenario of thermal attack with top metal layer temperature. We have demonstrated the leakage of the encryption key in an 128-bit AES chip using both proposed tile-based temperature calculations and top metal wire temperature calculations, quantified by simulation MTD (Measurements-to-Disclosure).","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"40 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125737595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1