2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第2页

Gate Voltage Optimization in Capacitive DC-DC Converters for Thermoelectric Energy Harvesting 热电能量收集电容式DC-DC变换器的栅极电压优化

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431654

Y. Tan, Y. Shiiki, H. Ishikuro

引用次数: 0

TCI Tester: Tester for Through Chip Interface TCI测试仪:通片接口测试仪

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431660

Hideto Kayashima, H. Amano

引用次数: 0

Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures 通过特定技术的NoC路由器架构弥合异构3D soc的频率差距

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431421

J. Joseph, Lennart Bamberg, Geonhwa Jeong, Ruei-Ting Chien, R. Leupers, A. García-Ortiz, T. Krishna, Thilo Pionteck

{"title":"Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures","authors":"J. Joseph, Lennart Bamberg, Geonhwa Jeong, Ruei-Ting Chien, R. Leupers, A. García-Ortiz, T. Krishna, Thilo Pionteck","doi":"10.1145/3394885.3431421","DOIUrl":"https://doi.org/10.1145/3394885.3431421","url":null,"abstract":"In heterogeneous 3D System-on-Chips (SoCs), NoCs with uniform properties suffer one major limitation; the clock frequency of routers varies due to different manufacturing technologies. For example, digital nodes allow for a higher clock frequency of routers than mixed-signal nodes. This large frequency gap is commonly tackled by complex and expensive pseudo-mesochronous or asynchronous router architectures. Here, a more efficient approach is chosen to bridge the frequency gap. We propose to use a heterogeneous network architecture. We show that reducing the number of VCs allows to bridge a frequency gap of up to 2×. We achieve a system-level latency improvement of up to 47% for uniform random traffic and up to 59% for PARSEC benchmarks, a maximum throughput increase of 50%, up to 68% reduced area and 38% reduced power in an exemplary setting combining 15-nm digital and 30-nm mixed-signal nodes and comparing against a homogeneous synchronous network architecture. Versus asynchronous and pseudo-mesochronous router architectures, the proposed optimization consistently performs better in area, in power and the average flit latency improvement can be larger than 51%.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132397654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Interference-Free Design Methodology for Paper-Based Digital Microfluidic Biochips 基于纸张的数字微流控生物芯片的无干扰设计方法

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431609

Yun-Chen Lo, Bing Li, Sooyong Park, K. Shin, Tsung-Yi Ho

{"title":"Interference-Free Design Methodology for Paper-Based Digital Microfluidic Biochips","authors":"Yun-Chen Lo, Bing Li, Sooyong Park, K. Shin, Tsung-Yi Ho","doi":"10.1145/3394885.3431609","DOIUrl":"https://doi.org/10.1145/3394885.3431609","url":null,"abstract":"Paper-based digital microfluidic biochips (P-DMFBs) have recently attracted great attention for its low-cost, in-place, and fast fabrication. This technology is essential for agile bio-assay development and deployment. P-DMFBs print electrodes and associate control lines on paper to control droplets and complete bio-assays. However, P-DMFBs have following issues: 1) control line interference may cause unwanted droplet movements, 2) avoiding control interference degrades assay performance and routability, 3) single layer fabrication limits routability, and 4) expensive ink cost limits low-cost benefits of P-DMFBs. To solve above issues, this work proposes an interference-free design methodology to design P-DMFBs with fast assay speed, better routability, and compact printing area. The contributions are as follows: First, we categorize control interference into soft and hard. Second, we identify only soft interference happens and propose to remove soft control interference constraints. Third, we propose an interference-free design methodology. Finally, we propose a cost-efficient ILP-based fluidic design module. Experimental results show proposed method outperforms prior work [14] across all bio-assay benchmarks. Compared to previous work, our cost-optimized designs use only 47%~78% area, gain 3.6%~16.2% more routing resources, and achieve 0.97x~1.5x shorter assay completion time. Our performance-optimized designs can accelerate assay speed by 1.05x~1.65x using 81%~96% printed area.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115698816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Robustness of Neuromorphic Computing with RRAM-based Crossbars and Optical Neural Networks 基于随机存储器的交叉棒和光神经网络的神经形态计算鲁棒性

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431634

Grace Li Zhang, Bing Li, Ying Zhu, Tianchen Wang, Yiyu Shi, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Tsung-Yi Ho, Ulf Schlichtmann, Xunzhao, Yin

{"title":"Robustness of Neuromorphic Computing with RRAM-based Crossbars and Optical Neural Networks","authors":"Grace Li Zhang, Bing Li, Ying Zhu, Tianchen Wang, Yiyu Shi, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Tsung-Yi Ho, Ulf Schlichtmann, Xunzhao, Yin","doi":"10.1145/3394885.3431634","DOIUrl":"https://doi.org/10.1145/3394885.3431634","url":null,"abstract":"RRAM-based crossbars and optical neural networks are attractive platforms to accelerate neuromorphic computing. However, both accelerators suffer from hardware uncertainties such as process variations. These uncertainty issues left unaddressed, the inference accuracy of these computing platforms can degrade significantly. In this paper, a statistical training method where weights under process variations and noise are modeled as statistical random variables is presented. To incorporate these statistical weights into training, the computations in neural networks are modified accordingly. For optical neural networks, we modify the cost function during software training to reduce the effects of process variations and thermal imbalance. In addition, the residual effects of process variations are extracted and calibrated in hardware test, and thermal variations on devices are also compensated in advance. Simulation results demonstrate that the inference accuracy can be improved significantly under hardware uncertainties for both platforms.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115971227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Mutation-based Compliance Testing for RISC-V 基于突变的RISC-V一致性测试

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431584

V. Herdt, Sören Tempel, Daniel Große, R. Drechsler

引用次数: 6

Deep Learning for Mask Synthesis and Verification: A Survey 基于深度学习的掩模合成与验证研究综述

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431624

Yibo Lin

引用次数: 0

Accurate and Efficient Simulation of Microfluidic Networks 微流控网络的精确高效仿真

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431608

G. Fink, Philipp Ebner, M. Hamidović, W. Haselmayr, R. Wille

引用次数: 8

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits AQFP超导电路的代数和布尔优化方法

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431606

Eleonora Testa, Siang-Yun Lee, Heinz Riener, G. Micheli

{"title":"Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits","authors":"Eleonora Testa, Siang-Yun Lee, Heinz Riener, G. Micheli","doi":"10.1145/3394885.3431606","DOIUrl":"https://doi.org/10.1145/3394885.3431606","url":null,"abstract":"Adiabatic quantum-flux-parametron (AQFP) circuits are a family of superconducting electronic (SCE) circuits that have recently gained growing interest due to their low-energy consumption, and may serve as alternative technology to overcome the down-scaling limitations of CMOS. AQFP logic design differs from classic digital design because logic cells are natively abstracted by the majority function, require data and clocking in specific timing windows, and have fan-out limitations. We describe here a novel majority-based logic synthesis flow addressing AQFP technology. In particular, we present both algebraic and Boolean methods over majority-inverter graphs (MIGs) aiming at optimizing size and depth of logic circuits. The technology limitations and constraints of the AQFP technology (e.g., path balancing and maximum fanout) are considered during optimization. The experimental results show that our flow reduces both size and depth of MIGs, while meeting the constraint of the AQFP technology. Further, we show an improvement for both area and delay when the MIGs are mapped into the AQFP technology.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125669988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept 具有大动态范围和自动化多周期概念的18位时间-数字转换器设计

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2021-01-18 DOI: 10.1145/3394885.3431643

Peter Toth, H. Ishikuro

引用次数: 1