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NVSim-VXs: An improved NVSim for variation aware STT-RAM simulation NVSim- vx:一种改进的NVSim，用于变化感知的STT-RAM仿真
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898053
Enes Eken, Linghao Song, Ismail Bayram, Cong Xu, Wujie Wen, Yuan Xie, Yiran Chen
{"title":"NVSim-VXs: An improved NVSim for variation aware STT-RAM simulation","authors":"Enes Eken, Linghao Song, Ismail Bayram, Cong Xu, Wujie Wen, Yuan Xie, Yiran Chen","doi":"10.1145/2897937.2898053","DOIUrl":"https://doi.org/10.1145/2897937.2898053","url":null,"abstract":"Spin-transfer torque random access memory (STT-RAM) recently received significant attentions for its promising characteristics in cache and memory applications. As an early-stage modeling tool, NVSim has been widely adopted for simulations of emerging nonvolatile memory technologies in computer architecture research, including STT-RAM, ReRAM, PCM, etc. In this work, we introduce a new member of NVSim family - NVSim-VXs, which enables statistical simulation of STT-RAM for write performance, errors, and energy consumption. This enhanced model takes into account the impacts of parametric variabilities of CMOS and MTJ devices and the chip operating temperature. It is also calibrated with Monte-Carlo Simulations based on macro-magnetic and SPICE models, covering five technology nodes between 22nm and 90nm. NVSim-VXs strongly supports the fast-growing needs of STT-RAM research on reliability analysis and enhancement, announcing the next important stage of NVSim development.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121326496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Notifying memories: A case-study on data-flow applications with NoC interfaces implementation 通知内存:使用NoC接口实现的数据流应用程序的案例研究
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898051
Kevin J. M. Martin, Mostafa Rizk, Martha Johanna Sepúlveda, J. Diguet
{"title":"Notifying memories: A case-study on data-flow applications with NoC interfaces implementation","authors":"Kevin J. M. Martin, Mostafa Rizk, Martha Johanna Sepúlveda, J. Diguet","doi":"10.1145/2897937.2898051","DOIUrl":"https://doi.org/10.1145/2897937.2898051","url":null,"abstract":"NoC-based architectures overcome the limitations of traditional buses by exploiting parallelism and offer large band-widths. NoC adoption also increases communication latency, which is especially penalising for data-flow applications (DF). We introduce the notifying memories (NM) concept to reduce this overhead. Our original approach eliminates useless memory requests. This paper demonstrates NM in the context of video coding applications implemented with dynamic DF. We have conducted cycle accurate systemC simulation of the NoC on an MPEG4 decoder to evaluate NM efficiency. The results show significant reductions in terms of latency (78%), injection rate (60%), and power savings (49%) along with throughput improvement (16%).","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125729673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
MTJ variation monitor-assisted adaptive MRAM write MTJ变化监测辅助的自适应MRAM写入
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2897979
Shaodi Wang, Hochul Lee, C. Grezes, P. Khalili, Kang L. Wang, Puneet Gupta
{"title":"MTJ variation monitor-assisted adaptive MRAM write","authors":"Shaodi Wang, Hochul Lee, C. Grezes, P. Khalili, Kang L. Wang, Puneet Gupta","doi":"10.1145/2897937.2897979","DOIUrl":"https://doi.org/10.1145/2897937.2897979","url":null,"abstract":"Spin-transfer torque random access memory (STT-RAM) and magnetoelectric random access memory (MeRAM) are promising non-volatile memory technologies. But STT-RAM and MeRAM both suffer from high write error rate due to thermal fluctuation of magnetization. Temperature and wafer-level process variation significantly exacerbate these problems. In this paper, we propose a design that adaptively selects optimized write pulse for STT-RAM and MeRAM to overcome ambient process and temperature variation. To enable the adaptive write, we design specific MTJ-based variation monitor, which precisely senses process and temperature variation. The monitor is over 10X faster, 5X more energy-efficient, and 20X smaller compared with conventional thermal monitors of similar accuracy. With adaptive write, the write latency of STT-RAM and MeRAM cache are reduced by up to 17% and 59% respectively, and application run time is improved by up to 41%.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"79 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126934438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis 利用常规逻辑综合解锁可逆逻辑综合的效率和可扩展性
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898107
Mathias Soeken, A. Chattopadhyay
{"title":"Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis","authors":"Mathias Soeken, A. Chattopadhyay","doi":"10.1145/2897937.2898107","DOIUrl":"https://doi.org/10.1145/2897937.2898107","url":null,"abstract":"Latest quantum technologies promise realization of extremely large circuits, whereas, reversible logic synthesis, the key automation step for quantum computing, suffers from scalability bottleneck. Scalability can be achieved with Decision Diagram (DD)-based synthesis at the cost of significant ancilla/garbage lines overhead. In this paper, we present a novel hierarchical reversible logic synthesis, where DD-based synthesis is invoked within an And-Inverter Graph (AIG)-based synthesis wrapper, balancing scalability and performance. The resulting tool can synthesize much larger functions (512-inputs), provides excellent flexibility, and restricts ancilla overhead. On average, line-count and gate-count reductions of 94% and 35% respectively, are achieved, compared to state-of-the-art.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"1530 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127445438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM MLC STT-RAM寿命和性能改进的两步状态转移最小化
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898106
Huizhang Luo, J. Hu, Liang Shi, C. Xue, Qingfeng Zhuge
{"title":"Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM","authors":"Huizhang Luo, J. Hu, Liang Shi, C. Xue, Qingfeng Zhuge","doi":"10.1145/2897937.2898106","DOIUrl":"https://doi.org/10.1145/2897937.2898106","url":null,"abstract":"Spin-transfer torque random access memory (STT-RAM) is considered as a promising candidate to replace SRAM as the next generation cache memory since it has better scalability and lower leakage power. Recently, 2-bit multi-level cell (MLC) STT-RAM has been proposed to further increase data density. However, a key drawback for MLC STT-RAM is that the magnetization directions of its hard and soft domains cannot be flipped to two opposite directions simultaneously, which leads to the two-step problem in state transitions. Two-step state transitions would significantly impact the lifetime of MLC STT-RAM due to the wasted flips in the soft domains. To solve the problem, this paper proposes a novel two-step state transition minimization (TSTM) scheme, to improve the lifetime of MLC STT-RAM when it is employed in cache design. The basic idea is by sacrificing certain cells as auxiliary flags, the two-step state transitions in STT-RAM can be well eliminated. Experimental results show that the proposed scheme can improve the lifetime of MLC STT-RAM to 318.5%.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134355118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Efficient performance modeling of analog integrated circuits via kernel density based sparse regression 基于核密度稀疏回归的模拟集成电路高效性能建模
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898013
Chenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li
{"title":"Efficient performance modeling of analog integrated circuits via kernel density based sparse regression","authors":"Chenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li","doi":"10.1145/2897937.2898013","DOIUrl":"https://doi.org/10.1145/2897937.2898013","url":null,"abstract":"With the aggressive scaling of integrated circuit technology, analog performance modeling is facing enormous challenges due to high-dimensional variation space and expensive transistor-level simulation. In this paper, we propose a kernel density based sparse regression algorithm (KDSR) to accurately fit analog performance models where the modeling error is not simply Gaussian due to strong nonlinearity. The key idea of KDSR is to approximate the non-Gaussian likelihood function by using non-parametric kernel density estimation. Furthermore, we adopt Laplace distribution as our prior knowledge to enforce a sparse pattern for model coefficients. The unknown model coefficients are finally determined by using an EM type algorithm for maximum-a-posteriori (MAP) estimation. Our proposed method can be viewed as an iterative and weighted sparse regression algorithm that aims to reduce the estimation bias for model coefficients due to outliers. Our experimental results demonstrate that our proposed KDSR method can achieve superior accuracy over the conventional sparse regression method.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134049265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Integration of multi-sensor occupancy grids into automotive ECUs 汽车ecu中多传感器占用网格的集成
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898035
T. Rakotovao, Julien Mottin, D. Puschini, C. Laugier
{"title":"Integration of multi-sensor occupancy grids into automotive ECUs","authors":"T. Rakotovao, Julien Mottin, D. Puschini, C. Laugier","doi":"10.1145/2897937.2898035","DOIUrl":"https://doi.org/10.1145/2897937.2898035","url":null,"abstract":"Occupancy Grids (OGs) are a popular framework for robotic perception. They were recently adopted for performing multisensor fusion and environment mapping for autonomous vehicles. However, high computational requirements strongly hinder their integration into less powerful automotive ECUs. To overcome this problem, we propose an algorithmic improvement for mapping range measurements into OGs. Experiments were conducted on a vehicle equipped with 16 LIDAR scans. Results demonstrate that a single-core ARM cortex A9 can build now in real-time OGs that map urban traffic scenarios of 100m-by-100m.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134285492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Accelerating soft-error-rate (SER) estimation in the presence of single event transients 加速单事件瞬态下的软错误率估计
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2897976
Ji Li, J. Draper
{"title":"Accelerating soft-error-rate (SER) estimation in the presence of single event transients","authors":"Ji Li, J. Draper","doi":"10.1145/2897937.2897976","DOIUrl":"https://doi.org/10.1145/2897937.2897976","url":null,"abstract":"Radiation-induced soft errors have posed an ever increasing reliability challenge as device dimensions keep shrinking in advanced CMOS technology. Therefore, it is imperative to devise fast and accurate soft error rate (SER) estimation methods. Previous works mainly focus on improving the accuracy of the SER results, whereas the speed improvement is limited to partitioning and parallel processing. This paper presents an efficient SER estimation framework for combinational logic circuits in the presence of single-event transients (SETs). A novel top-down memoization algorithm is proposed to accelerate the propagation of SETs. Experimental results of a variety of benchmark circuits demonstrate that the proposed approach achieves up to 560.2X times speedup with less than 3% difference in terms of SER results compared with the baseline algorithm.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129527682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Physics-based full-chip TDDB assessment for BEOL interconnects 基于物理的BEOL互连全芯片TDDB评估
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898062
Xin Huang, V. Sukharev, Zhongdong Qi, Taeyoung Kim, S. Tan
{"title":"Physics-based full-chip TDDB assessment for BEOL interconnects","authors":"Xin Huang, V. Sukharev, Zhongdong Qi, Taeyoung Kim, S. Tan","doi":"10.1145/2897937.2898062","DOIUrl":"https://doi.org/10.1145/2897937.2898062","url":null,"abstract":"As technology advances, Time-Dependent Dielectric Breakdown (TDDB) has become one of the major reliability threats for Copper/low-k interconnects. This article presents a novel approach, techniques, and flow for the physics-based chip-scale assessment of backend low-k TDDB. In our work, the breakdown development is considered as the complementary combination of electric current path generation by means of diffusing metal ions and field-based hoping conductivity of the current carriers. It replaces the widely accepted across-layout electrostatic field based TDDB assessment. As a result, the model generated time-to-failure (TTF) is governed by kinetics of the electric current path generation, which is controlled by a time-dependent minimum metal ion concentration in the inter-metal dielectrics (IMD) gap-fill. Finite element analysis (FEA)-based simulations are used for populating the set of lookup tables, which provide a time to breakdown for any interconnect pattern with given geometries and voltages. A pattern-matching technique is used for extracting from the layout all patterns belonging to different classes of pattern shapes with different geometries, locations and electric loads. Experimental results obtained on a test chip show that upon the calibration the proposed flow provides a capability to evaluate chip-scale low-k TDDB reliability based on the calculated TTF and detect most leaking shapes in the layout.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129263855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks 基于随机计算的深度神经网络动态能量-精度权衡
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898011
Kyounghoon Kim, Jungki Kim, Joonsang Yu, J. Seo, Jongeun Lee, Kiyoung Choi
{"title":"Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks","authors":"Kyounghoon Kim, Jungki Kim, Joonsang Yu, J. Seo, Jongeun Lee, Kiyoung Choi","doi":"10.1145/2897937.2898011","DOIUrl":"https://doi.org/10.1145/2897937.2898011","url":null,"abstract":"This paper presents an efficient DNN design with stochastic computing. Observing that directly adopting stochastic computing to DNN has some challenges including random error fluctuation, range limitation, and overhead in accumulation, we address these problems by removing near-zero weights, applying weight-scaling, and integrating the activation function with the accumulator. The approach allows an easy implementation of early decision termination with a fixed hardware design by exploiting the progressive precision characteristics of stochastic computing, which was not easy with existing approaches. Experimental results show that our approach outperforms the conventional binary logic in terms of gate area, latency, and power consumption.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115357442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 137
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