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2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)最新文献

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Utilization bounds on allocating rate-monotonic scheduled multi-mode tasks on multiprocessor systems 多处理机系统上分配速率单调调度多模式任务的利用率界限
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898108
Wen-Hung Huang, Jian-Jia Chen
{"title":"Utilization bounds on allocating rate-monotonic scheduled multi-mode tasks on multiprocessor systems","authors":"Wen-Hung Huang, Jian-Jia Chen","doi":"10.1145/2897937.2898108","DOIUrl":"https://doi.org/10.1145/2897937.2898108","url":null,"abstract":"Formal models used for representing recurrent real-time processes have traditionally been characterized by a collection of jobs that are released periodically. However, such a modeling may result in resource under-utilization in systems whose behaviors are not entirely periodic. For instance, tasks in cyber-physical system (CPS) may change their service levels, e.g., periods and/or execution times, to adapt to the changes of environments. In this work, we study a model that is a generalization of the periodic task model, called multi-mode task model: a task has several modes specified with different execution times and periods to switch during runtime, independent of other tasks. Moreover, we study the problem of allocating a set of multi-mode tasks on a homogeneous multiprocessor system. We present a scheduling algorithm using any reasonable allocation decreasing (RAD) algorithm for task allocations for scheduling multi-mode tasks on multiprocessor systems. We prove that this algorithm achieves 38% utilization for implicit-deadline rate-monotonic (RM) scheduled multi-mode tasks on multiprocessor systems.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114256686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Invited: Approximate computing with partially unreliable dynamic random access memory — Approximate DRAM
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2905002
Matthias Jung, Deepak M. Mathew, C. Weis, N. Wehn
{"title":"Invited: Approximate computing with partially unreliable dynamic random access memory — Approximate DRAM","authors":"Matthias Jung, Deepak M. Mathew, C. Weis, N. Wehn","doi":"10.1145/2897937.2905002","DOIUrl":"https://doi.org/10.1145/2897937.2905002","url":null,"abstract":"In the context of approximate computing, Approximate Dynamic Random Access Memory (ADRAM) enables the tradeoff between energy efficiency, performance and reliability. The inherent error resilience of applications allows sacrificing data storage robustness and stability by lowering the refresh rate or disabling refresh in DRAMs completely. Consequently, it is important to know exactly the statistical DRAM behavior with respect to retention time, process variation and temperature to manage this trade-off and thereby deliberately exploiting the error resilience of different target applications.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131529823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Invited: Wireless sensor nodes for environmental monitoring in Internet of Things 特邀嘉宾:物联网环境监测无线传感器节点
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898602
Ting Lu, Li-Ren Huang, Yu Lee, Kun-Ju Tsai, Y. Liao, N. Cheng, Yuan-Hua Chu, Y. Tsai, Fang-Chu Chen, T. Chiueh
{"title":"Invited: Wireless sensor nodes for environmental monitoring in Internet of Things","authors":"Ting Lu, Li-Ren Huang, Yu Lee, Kun-Ju Tsai, Y. Liao, N. Cheng, Yuan-Hua Chu, Y. Tsai, Fang-Chu Chen, T. Chiueh","doi":"10.1145/2897937.2898602","DOIUrl":"https://doi.org/10.1145/2897937.2898602","url":null,"abstract":"This paper presents a self-sustainable landslide surveillance system that detects hazardous water content level in soils and provides real-time landslide warnings to residents, without requiring wired electricity transmission. A self-powered soil water content sensor was applied as the trigger of alert event. It solves the energy supply problem by an environmental interrupt mechanism, which wakes up the sensor and communication circuits in a sensing node only when the water content in monitored soils exceeds a certain threshold, and thus completely eliminates the need for an ALS node to periodically wake up, sense and communicate. By tightly integrating energy harvesting, environment sensing and circuit wake-up, it may well be the most energy-efficient landslide surveillance system designed to monitor water content in soils in the world.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130752334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
PDS: Pseudo-differential sensing scheme for STT-MRAM PDS: STT-MRAM伪差分传感方案
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898058
W. Kang, Tingting Pang, Bi Wu, Weifeng Lv, Youguang Zhang, Guangyu Sun, Weisheng Zhao
{"title":"PDS: Pseudo-differential sensing scheme for STT-MRAM","authors":"W. Kang, Tingting Pang, Bi Wu, Weifeng Lv, Youguang Zhang, Guangyu Sun, Weisheng Zhao","doi":"10.1145/2897937.2898058","DOIUrl":"https://doi.org/10.1145/2897937.2898058","url":null,"abstract":"STT-MRAM has been considered as one of the most promising nonvolatile memory candidates in the next-generation of computer architecture. However, the read reliability and dynamic write power concerns greatly hinder its practical application. In this paper, we propose a synergistic solution, namely pseudo-differential sensing (PDS), to jointly address these two concerns. Three techniques, including cell cluster, asymmetric sensing amplifier (ASA) and self-error-detection-correction (SEDC), are proposed to implement the PDS concept. Our experimental results show that the PDS scheme with the 3T3MTJ cell cluster can reduce the area (~21.7%) and write power (~25.6%) of the differential sensing (DS) scheme while improve the read reliability (read margin, ~35.6%) of the typical sensing (TS) scheme for a 16 Mbit cache. Furthermore, the PDS scheme with the 1T3MTJ cell cluster can outperform both the TS and DS schemes in terms of area (~40.0%, ~66.1%), read latency (~16.6%, ~32.1%), read power (~16.7%, ~37.1%), write latency (~5.4%, 16.3%) and write power (~18.6%, ~43.4%).","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131116916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
ageOpt-RMT: Compiler-driven variation-aware aging optimization for redundant multithreading ageOpt-RMT:针对冗余多线程的编译器驱动的变量感知老化优化
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2897980
F. Kriebel, Semeen Rehman, M. Shafique, J. Henkel
{"title":"ageOpt-RMT: Compiler-driven variation-aware aging optimization for redundant multithreading","authors":"F. Kriebel, Semeen Rehman, M. Shafique, J. Henkel","doi":"10.1145/2897937.2897980","DOIUrl":"https://doi.org/10.1145/2897937.2897980","url":null,"abstract":"Reliability optimization in the nano-era needs to account for multiple reliability concerns. Redundant Multithreading (RMT) has emerged as a promising technique to mitigate soft-errors in multi-cores. Since variation- and aging-unawareness during RMT may increase aging of slow cores due to high utilization or lead to unbalanced aging under varying workload scenarios, we propose to leverage variations in vulnerability and duty cycle by means of multiple compiled versions. We perform variation-aware task mapping to proactively reduce the aging of slower cores and thereby maintaining the minimum processing capabilities. Afterwards, we perform an aging-aware activation/deactivation of RMT considering tasks' variable resilience properties and select appropriate reliable versions for the mapped tasks. Experimental results demonstrate that compared to state-of-the-art aging-unaware RMT techniques, our ageOpt-RMT provides improved and balanced aging profiles by 2x on average.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121590435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Simplifying deep neural networks for neuromorphic architectures 为神经形态架构简化深度神经网络
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898092
Jaeyong Chung, T. Shin
{"title":"Simplifying deep neural networks for neuromorphic architectures","authors":"Jaeyong Chung, T. Shin","doi":"10.1145/2897937.2898092","DOIUrl":"https://doi.org/10.1145/2897937.2898092","url":null,"abstract":"Deep learning using deep neural networks is taking machine intelligence to the next level in computer vision, speech recognition, natural language processing, etc. Brain-like hardware platforms for the brain-inspired computational models are being studied, but none of such platforms deals with the huge size of practical deep neural networks. This paper presents two techniques, factorization and pruning, that not only compress the models but also maintain the form of the models for the execution on neuromorphic architectures. We also propose a novel method to combine the two techniques. The proposed method shows significant improvements in reducing the number of model parameters over standalone use of each method while maintaining the performance. Our experimental results show that the proposed method can achieve 31 x reduction rate without loss of accuracy for the largest layer of AlexNet.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121681166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Exploiting design-for-debug for flexible SoC security architecture 利用面向调试的设计实现灵活的SoC安全架构
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898020
A. Basak, S. Bhunia, S. Ray
{"title":"Exploiting design-for-debug for flexible SoC security architecture","authors":"A. Basak, S. Bhunia, S. Ray","doi":"10.1145/2897937.2898020","DOIUrl":"https://doi.org/10.1145/2897937.2898020","url":null,"abstract":"Systematic implementation of System-on-Chip (SoC) security policies typically involves smart wrappers extracting local security critical events of interest from Intellectual Property (IP) blocks, together with a control engine that communicates with the wrappers to analyze the events for policy adherence. However, developing customized wrappers at each IP for security requirements may incur significant overhead in area and hardware resources. In this paper, we address this problem by exploiting the extensive design-fordebug (DfD) instrumentation already available on-chip. In addition to reduction in the overall hardware overhead, the approach also adds flexibility to the security architecture itself, e.g., permitting use of on-field DfD instrumentation, survivability and control hooks to patch security policy implementation in response to bugs and attacks found at postsilicon or changing security requirements on-field. We show how to design scalable interface between security and debug architectures that provides the benefits of flexibility to security policy implementation without interfering with existing debug and survivability use cases and at minimal additional cost in energy and design complexity.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"280 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115601930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Shift sprinting: Fine-grained temperature-aware NoC-based MCSoC architecture in dark silicon age Shift冲刺:暗硅时代细粒度温度感知的基于noc的MCSoC架构
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898090
Amin Rezaei, Danella Zhao, M. Daneshtalab, Hongyi Wu
{"title":"Shift sprinting: Fine-grained temperature-aware NoC-based MCSoC architecture in dark silicon age","authors":"Amin Rezaei, Danella Zhao, M. Daneshtalab, Hongyi Wu","doi":"10.1145/2897937.2898090","DOIUrl":"https://doi.org/10.1145/2897937.2898090","url":null,"abstract":"Reliability is a critical feature of chip integration and unreliability can lead to performance, cost, and time-to-market penalties. Moreover, upcoming Many-Core System-on-Chips (MCSoCs), notably future generations of mobile devices, will suffer from high power densities due to the dark silicon problem. Thus, in this paper, a novel NoC-based MCSoC architecture, called Shift Sprinting, is introduced in order to reliably utilize dark silicon under the power budget constraint. By employing the concept of distributional sprinting, our proposed architecture provides Quality of Service (QoS) to efficiently run real-time streaming applications in mobile devices. Simulation results show meaningful gain in performance and reliability of the system compared to state-of-the-art works.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122876434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
SecDCP: Secure dynamic cache partitioning for efficient timing channel protection SecDCP:安全的动态缓存分区，用于有效的定时通道保护
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898086
Yao Wang, Andrew Ferraiuolo, Danfeng Zhang, A. Myers, G. Suh
{"title":"SecDCP: Secure dynamic cache partitioning for efficient timing channel protection","authors":"Yao Wang, Andrew Ferraiuolo, Danfeng Zhang, A. Myers, G. Suh","doi":"10.1145/2897937.2898086","DOIUrl":"https://doi.org/10.1145/2897937.2898086","url":null,"abstract":"In today's multicore processors, the last-level cache is often shared by multiple concurrently running processes to make efficient use of hardware resources. However, previous studies have shown that a shared cache is vulnerable to timing channel attacks that leak confidential information from one process to another. Static cache partitioning can eliminate the cache timing channels but incurs significant performance overhead. In this paper, we propose Secure Dynamic Cache Partitioning (SecDCP), a partitioning technique that defeats cache timing channel attacks. The SecDCP scheme changes the size of cache partitions at run time for better performance while preventing insecure information leakage between processes. For cache-sensitive multiprogram workloads, our experimental results show that SecDCP improves performance by up to 43% and by an average of 12.5% over static cache partitioning.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124736731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 104
GarbledCPU: A MIPS processor for secure computation in hardware GarbledCPU:硬件中用于安全计算的MIPS处理器
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898027
Ebrahim M. Songhori, Shaza Zeitouni, Ghada Dessouky, T. Schneider, A. Sadeghi, F. Koushanfar
{"title":"GarbledCPU: A MIPS processor for secure computation in hardware","authors":"Ebrahim M. Songhori, Shaza Zeitouni, Ghada Dessouky, T. Schneider, A. Sadeghi, F. Koushanfar","doi":"10.1145/2897937.2898027","DOIUrl":"https://doi.org/10.1145/2897937.2898027","url":null,"abstract":"We present GarbledCPU, the first framework that realizes a hardware-based general purpose sequential processor for secure computation. Our MIPS-based implementation enables development of applications (functions) in a high-level language while performing secure function evaluation (SFE) using Yao's garbled circuit protocol in hardware. GarbledCPU provides three degrees of freedom for SFE which allow leveraging the trade-off between privacy and performance: public functions, private functions, and semi-private functions. We synthesize GarbledCPU on a Virtex-7 FPGA as a proof-of-concept implementation and evaluate it on various benchmarks including Hamming distance, private set intersection and AES. Our results indicate that our pipelined hardware framework outperforms the fastest available software implementation.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125590515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
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