2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)最新文献

Invited: Ultra low power integrated transceivers for near-field IoT 诚邀:近场物联网超低功耗集成收发器

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2907024

M. Sanduleanu, I. Elfadel

引用次数: 5

Dot-product engine for neuromorphic computing: Programming 1T1M crossbar to accelerate matrix-vector multiplication 神经形态计算的点积引擎:编程1T1M交叉栏加速矩阵向量乘法

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898010

Miao Hu, J. Strachan, Zhiyong Li, E. M. Grafals, N. Dávila, Catherine E. Graves, Sity Lam, Ning Ge, Jianhua Joshua Yang, R. Williams

{"title":"Dot-product engine for neuromorphic computing: Programming 1T1M crossbar to accelerate matrix-vector multiplication","authors":"Miao Hu, J. Strachan, Zhiyong Li, E. M. Grafals, N. Dávila, Catherine E. Graves, Sity Lam, Ning Ge, Jianhua Joshua Yang, R. Williams","doi":"10.1145/2897937.2898010","DOIUrl":"https://doi.org/10.1145/2897937.2898010","url":null,"abstract":"Vector-matrix multiplication dominates the computation time and energy for many workloads, particularly neural network algorithms and linear transforms (e.g, the Discrete Fourier Transform). Utilizing the natural current accumulation feature of memristor crossbar, we developed the Dot-Product Engine (DPE) as a high density, high power efficiency accelerator for approximate matrix-vector multiplication. We firstly invented a conversion algorithm to map arbitrary matrix values appropriately to memristor conductances in a realistic crossbar array, accounting for device physics and circuit issues to reduce computational errors. The accurate device resistance programming in large arrays is enabled by close-loop pulse tuning and access transistors. To validate our approach, we simulated and benchmarked one of the state-of-the-art neural networks for pattern recognition on the DPEs. The result shows no accuracy degradation compared to software approach (99 % pattern recognition accuracy for MNIST data set) with only 4 Bit DAC/ADC requirement, while the DPE can achieve a speed-efficiency product of 1,000× to 10,000× compared to a custom digital ASIC.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"618 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120932828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 547

Strategy without tactics: Policy-agnostic hardware-enhanced control-flow integrity 没有策略的策略:与策略无关的硬件增强的控制流完整性

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898098

Dean Sullivan, Orlando Arias, Lucas Davi, Per Larsen, A. Sadeghi, Yier Jin

引用次数: 57

Serial T0: Approximate bus encoding for energy-efficient transmission of sensor signals 串行T0:用于传感器信号节能传输的近似总线编码

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898089

D. J. Pagliari, E. Macii, M. Poncino

引用次数: 19

Precise error determination of approximated components in sequential circuits with model checking 时序电路中近似元件的精确误差测定

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898069

Arun Chandrasekharan, Mathias Soeken, Daniel Große, R. Drechsler

引用次数: 37

Efficient transistor-level timing yield estimation via line sampling 有效的晶体管级时序良率估计通过线路采样

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898016

H. Awano, Takashi Sato

引用次数: 2

A probabilistic scheduling framework for mixed-criticality systems 混合临界系统的概率调度框架

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2897971

Alejandro Masrur

引用次数: 12

Comprehensive optimization of scan chain timing during late-stage IC implementation 集成电路后期实现中扫描链时序的全面优化

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2897998

K. Chung, A. Kahng, Jiajia Li

引用次数: 1

Lattice-based encryption over standard lattices in hardware 在硬件标准格之上的基于格的加密

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898037

James Howe, C. Rafferty, Máire O’Neill, F. Regazzoni, T. Güneysu, Kevin Beeden

{"title":"Lattice-based encryption over standard lattices in hardware","authors":"James Howe, C. Rafferty, Máire O’Neill, F. Regazzoni, T. Güneysu, Kevin Beeden","doi":"10.1145/2897937.2898037","DOIUrl":"https://doi.org/10.1145/2897937.2898037","url":null,"abstract":"Lattice-based cryptography has gained credence recently as a replacement for current public-key cryptosystems, due to its quantum-resilience, versatility, and relatively low key sizes. To date, encryption based on the learning with errors (LWE) problem has only been investigated from an ideal lattice standpoint, due to its computation and size efficiencies. However, a thorough investigation of standard lattices in practice has yet to be considered. Standard lattices may be preferred to ideal lattices due to their stronger security assumptions and less restrictive parameter selection process. In this paper, an area-optimised hardware architecture of a standard lattice-based cryptographic scheme is proposed. The design is implemented on a FPGA and it is found that both encryption and decryption fit comfortably on a Spartan-6 FPGA. This is the first hardware architecture for standard lattice-based cryptography reported in the literature to date, and thus is a benchmark for future implementations. Additionally, a revised discrete Gaussian sampler is proposed which is the fastest of its type to date, and also is the first to investigate the cost savings of implementing with A/2-bits of precision. Performance results are promising compared to the hardware designs of the equivalent ring-LWE scheme, which in addition to providing stronger security proofs; generate 1272 encryptions per second and 4395 decryptions per second.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128244204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 41

Hybrid STT-CMOS designs for reverse-engineering prevention 用于逆向工程预防的STT-CMOS混合设计

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2016-06-05 DOI: 10.1145/2897937.2898099

Theodore Winograd, H. Salmani, H. Mahmoodi, K. Gaj, H. Homayoun

{"title":"Hybrid STT-CMOS designs for reverse-engineering prevention","authors":"Theodore Winograd, H. Salmani, H. Mahmoodi, K. Gaj, H. Homayoun","doi":"10.1145/2897937.2898099","DOIUrl":"https://doi.org/10.1145/2897937.2898099","url":null,"abstract":"This paper presents a rigorous step towards design-for-assurance by introducing a new class of logically reconfigurable design resilient to design reverse engineering. Based on the non-volatile spin transfer torque (STT) magnetic technology, we introduce a basic set of non-volatile reconfigurable Look-Up-Table (LUT) logic components (NV-STT-based LUTs). STT-based LUT with significantly different set of characteristics compared to CMOS provides new opportunities to enhance design security yet makes it challenging to remain highly competitive with custom CMOS or even SRAM-based LUT in terms of power, performance and area. To address these challenges, we propose several algorithms to select and replace custom CMOS gates with reconfigurable STT-based LUTs during design implementation such that the functionality of STT-based components and therefore the entire design cannot be determined in any manageable time, rendering any design reverse engineering attack ineffective. Our study conducted on a large number of standard circuit benchmarks concludes significant resiliency of hybrid STT-CMOS circuits against various types of attacks. Furthermore, the selection algorithms on average have a small impact of less than 3%, 8%, and 3% on design parametric constraints including performance, power and area, respectively.","PeriodicalId":185271,"journal":{"name":"2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129260336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 43