Proceedings of the 2021 International Symposium on Physical Design最新文献_第2页

Snap-3D: A Constrained Placement-Driven Physical Design Methodology for Face-to-Face-Bonded 3D ICs Snap-3D:面对面键合3D集成电路的受限位置驱动物理设计方法

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3439706.3447049

Pruek Vanna-Iampikul, Chengjia Shao, Yi-Chen Lu, S. Pentapati, S. Lim

{"title":"Snap-3D: A Constrained Placement-Driven Physical Design Methodology for Face-to-Face-Bonded 3D ICs","authors":"Pruek Vanna-Iampikul, Chengjia Shao, Yi-Chen Lu, S. Pentapati, S. Lim","doi":"10.1145/3439706.3447049","DOIUrl":"https://doi.org/10.1145/3439706.3447049","url":null,"abstract":"3D integration technology is one of the leading options that can advance Moore's Law beyond conventional scaling. Due to the absence of commercial 3D placers and routers, existing 3D physical design flows rely heavily on 2D commercial tools to handle 3D IC physical synthesis. Specifically, these flows build 2D designs first and then convert them into 3D designs. However, several works demonstrate that design qualities degrade during this 2D-3D transformation. In this paper, we overcome this issue with our Snap-3D, a constraint-driven placement approach to build commercial-quality 3D ICs. Our key idea is based on the observation that if the standard cell height is contracted by one half and partitioned into multiple tiers, any commercial 2D placer can place them onto the row structure and naturally achieve high-quality 3D placement. This methodology is shown to optimize power, performance, and area (PPA) metrics across different tiers simultaneously and minimize the aforementioned design quality loss. Experimental results on 7 industrial designs demonstrate that Snap-3D achieves up to 5.4% wirelength, 10.1% power, and 92.3% total negative slack improvements compared with state-of-the-art 3D design flows.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124189753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs 一种可扩展且稳健的分层布局，可实现100k-LUT fpga的24小时原型设计

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3439706.3447047

Ganesh Gore, Xifan Tang, P. Gaillardon

{"title":"A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs","authors":"Ganesh Gore, Xifan Tang, P. Gaillardon","doi":"10.1145/3439706.3447047","DOIUrl":"https://doi.org/10.1145/3439706.3447047","url":null,"abstract":"Physical design for Field Programmable Gate Array (FPGA) is challenging and time-consuming, primarily due to the use of a full-custom approach for aggressively optimize Performance, Power and Area (P.P.A.) of the FPGA design. The growing number of FPGA applications demands novel architectures and shorter development cycles. The use of an automated toolchain is essential to reduce end-to-end development time. This paper presents scalable and adaptive hierarchical floorplanning strategies to significantly reduce the physical design runtime and enable millions-of-LUT FPGA layout implementations using standard ASIC toolchains. This approach mainly exploits the regularity of the design and performs necessary feedthrough creations for global and clock nets to eliminate any requirement of global optimizations. To validate this approach, we implemented full-chip layouts for modern FPGA fabric with logic capacity ranging from 40 to 100k LUTs using a commercial 12nm technology. Our results show that the physical implementation of a 128k-LUT FPGA fabric can be achieved within 24-hours, which has not been demonstrated by any previous work. Compared to previous work, the runtime reduction of 8x is obtained for implementing 2.5k LUTs FPGA device.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"355 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115931761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

The Law of Attraction: Affinity-Aware Placement Optimization using Graph Neural Networks 吸引力法则:使用图形神经网络的亲和性感知布局优化

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3439706.3447045

Yi-Chen Lu, S. Pentapati, S. Lim

引用次数: 19

ML-Based Wire RC Prediction in Monolithic 3D ICs with an Application to Full-Chip Optimization 基于ml的单片三维集成电路导线RC预测及其在全芯片优化中的应用

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3439706.3447266

S. Pentapati, B. W. Ku, S. Lim

{"title":"ML-Based Wire RC Prediction in Monolithic 3D ICs with an Application to Full-Chip Optimization","authors":"S. Pentapati, B. W. Ku, S. Lim","doi":"10.1145/3439706.3447266","DOIUrl":"https://doi.org/10.1145/3439706.3447266","url":null,"abstract":"The state-of-the-art Monolithic 3D (M3D) IC design methodologies~citem3d:Ku-tcad-Compact2D, m3d:Panth-tcad-Shrunk2D use commercial electronic design automation tools built for 2D ICs to implement a pseudo-3D design and split it into two dies that are routed independently to create an M3D design. Therefore, an accurate estimation of 3D wire parasitics at the pseudo-3D stage is important to achieve a well optimized M3D design. In this paper, we present a regression model based on boosted decision tree learning to better predict the 3D wire parasitics (RCs) at the pseudo-3D stage. Our model is trained using individual net features as well as the full-chip design metrics using multiple instantiations of 8 different netlists and is tested on 3 unseen netlists. Compared to the Compact-2D~citem3d:Ku-tcad-Compact2D flow on its own as the reference pseudo-3D, the addition of our predictive model achieves up to $2.9 times$ and $1.7 times$ smaller root mean square error in the resistance and capacitance predictions respectively. On an unseen netlist design, we observe that our model provides 98.6% and 94.6% RC prediction accuracy in 3D and up to $6.4 times$ smaller total negative slack of the design compared to the result of Compact-2D flow resulting in a more timing-robust M3D IC. This model is not limited to Compact-2D, and can be extended to other pseudo-3D flows.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125402829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Advances in Carbon Nanotube Technologies: From Transistors to a RISC-V Microprocessor 碳纳米管技术的进展:从晶体管到RISC-V微处理器

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3439706.3446897

G. Hills

引用次数: 0

Session details: Session 13: Contest and Results 会议详情:第13部分:竞赛和结果

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3457136

G. Posser

引用次数: 0

EDA and Quantum Computing: The key role of Quantum Circuits EDA与量子计算:量子电路的关键作用

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3439706.3446900

L. Stok

引用次数: 3

Physical Verification at Advanced Technology Nodes and the Road Ahead 先进技术节点的物理验证与未来道路

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3439706.3446901

J. Rey

引用次数: 0

The Physical Design of Biological Systems - Insights from the Fly Brain 生物系统的物理设计——来自苍蝇大脑的见解

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3439706.3446898

L. Scheffer

{"title":"The Physical Design of Biological Systems - Insights from the Fly Brain","authors":"L. Scheffer","doi":"10.1145/3439706.3446898","DOIUrl":"https://doi.org/10.1145/3439706.3446898","url":null,"abstract":"Many different physical substrates can support complex computation. This is particularly apparent when considering human made and biological systems that perform similar functions, such as visually guided navigation. In common, however, is the need for good physical design, as such designs are smaller, faster, lighter, and lower power, factors in both the jungle and the marketplace. Although the physical design of man-made systems is relatively well understood, the physical design of biological computation has remained murky due to a lack of detailed information on their construction. The recent EM (electron microscope) reconstruction of the central brain of the fruit fly now allows us to start to examine these issues. Here we look at the physical design of the fly brain, including such factors as fan-in and fanout, logic depth, division into physical compartments and how this affects electrical response, pin to computation ratios (Rent's rule), and other physical characteristics of at least one biological computation substrate. From this we speculate on how physical design algorithms might change if the target implementation was a biological neural network.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"15 11-12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134308833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Scalable System and Silicon Architectures to Handle the Workloads of the Post-Moore Era 处理后摩尔时代工作负载的可扩展系统和硅架构

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3439706.3446894

I. Bolsens

{"title":"Scalable System and Silicon Architectures to Handle the Workloads of the Post-Moore Era","authors":"I. Bolsens","doi":"10.1145/3439706.3446894","DOIUrl":"https://doi.org/10.1145/3439706.3446894","url":null,"abstract":"The end of Moore's law has been proclaimed on many occasions and it's probably safe to say that we are now working in the post-Moore era. But no one is ready to slow down just yet. We can view Gordon Moore's observation on transistor densification as just one aspect of a longer-term underlying technological trend - the Law of Accelerating Returns articulated by Kurzweil. Arguably, companies became somewhat complacent in the Moore era, happy to settle for the gains brought by each new process node. Although we can expect scaling to continue, albeit at a slower pace, the end of Moore's Law delivers a stronger incentive to push other trends harder. Some exciting new technologies are now emerging such as multi-chip 3D integration and the introduction of new technologies such as storage-class memory and silicon photonics. Moreover, we are also entering a golden age of computer architecture innovation. One of the key drivers is the pursuit of domain-specific architectures as proclaimed by Turing award winners John Hennessy and David Patterson. A good example is the Xilinx's AI Engine, one of the important features of the Versal? ACAP (adaptive compute acceleration platform). Today, the explosion of AI workloads is one of the most powerful drivers shifting our attention to find faster ways of moving data into, across, and out of accelerators. Features such as massive parallel processing elements, the use of domain specific accelerators, the dense interconnect between distributed on-chip memories and processing elements, are examples of the ways chip makers are looking beyond scaling to achieve next-generation performance gains.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115702721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0