Proceedings of the 2021 International Symposium on Physical Design最新文献

Reinforcement Learning for Placement Optimization 用于布局优化的强化学习

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3439706.3446883

Anna Goldie, Azalia Mirhoseini

{"title":"Reinforcement Learning for Placement Optimization","authors":"Anna Goldie, Azalia Mirhoseini","doi":"10.1145/3439706.3446883","DOIUrl":"https://doi.org/10.1145/3439706.3446883","url":null,"abstract":"In the past decade, computer systems and chips have played a key role in the success of artificial intelligence (AI). Our vision in Google Brain's Machine Learning for Systems team is to use AI to transform the way in which computer systems and chips are designed. Many core problems in systems and hardware design are combinatorial optimization or decision making tasks with state and action spaces that are orders of magnitude larger than that of standard AI benchmarks in robotics and games. In this talk, we will describe some of our latest learning based approaches to tackling such large-scale optimization problems. We will discuss our work on a new domain-transferable reinforcement learning (RL) method for optimizing chip placement [1], a long pole in hardware design. Our approach is capable of learning from past experience and improving over time, resulting in more optimized placements on unseen chip blocks as the RL agent is exposed to a larger volume of data. Our objective is to minimize power, performance, and area. We show that, in under six hours, our method can generate placements that are superhuman or comparable on modern accelerator chips, whereas existing baselines require human experts in the loop and can take several weeks.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114160424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Learning Point Clouds in EDA EDA中的学习点云

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3439706.3446895

Wei Li, Guojin Chen, Haoyu Yang, Ran Chen, Bei Yu

引用次数: 2

Session details: Session 8: Monolithic 3D and Packaging Session 会议细节:会议8:单片3D和包装会议

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3457132

B. Swartz

引用次数: 0

Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation At Advanced Process Nodes 在高级工艺节点上实现机器学习的高频低功耗数字设计

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3439706.3447043

S. Nath, Vishal Khandelwal

{"title":"Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation At Advanced Process Nodes","authors":"S. Nath, Vishal Khandelwal","doi":"10.1145/3439706.3447043","DOIUrl":"https://doi.org/10.1145/3439706.3447043","url":null,"abstract":"Relentless pursuit of high-frequency low-power designs at advanced nodes necessitate achieving signoff-quality timing and power during digital implementation to minimize any over-design. With growing design sizes (1--10M instances), full flow runtime is an equally important metric and commercial implementation tools use graph-based timing analysis (GBA) to gain runtime over path-based timing analysis (PBA), at the cost of pessimism in timing. Last mile timing and power closure is then achieved through expensive PBA-driven engineering change order (ECO) loops in signoff stage. In this work, we explore \"on-the-fly'' machine learning (ML) models to predict PBA timing based on GBA features, to drive digital implementation flow. Our ML model reduces the GBA vs. PBA pessimism with minimal runtime overhead, resulting in improved area/power without compromising on signoff timing closure. Experimental results obtained by integrating our technique in a commercial digital implementation tool show improvement of up to 0.92% in area, 11.7% and 1.16% in power in leakage- and total power-centric designs, respectively. Our method has a runtime overhead of $sim$3% across a suite of 5--16nm industrial designs.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127419738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Physical Design Challenges and Solutions for Emerging Heterogeneous 3D Integration Technologies 新兴异构3D集成技术的物理设计挑战和解决方案

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3439706.3446903

Lingjun Zhu, S. Lim

引用次数: 0

Session details: Session 1: Opening Session and First Keynote 会议详情:第一部分:开幕式和第一主题演讲

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3457126

J. Lienig

引用次数: 0

Session details: Session 2: Machine Learning for Physical Design (1/2) 会议详情:第二部分:物理设计中的机器学习(1/2)

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3457127

Jiang Hu

引用次数: 0

Session details: Session 9: Brains, Computers and EDA 会议详情:第9部分:大脑、计算机和EDA

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3457133

P. Groeneveld

引用次数: 0

Physical Design for 3D Chiplets and System Integration 三维小芯片的物理设计与系统集成

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3439706.3446881

Frank J. C. Lee

{"title":"Physical Design for 3D Chiplets and System Integration","authors":"Frank J. C. Lee","doi":"10.1145/3439706.3446881","DOIUrl":"https://doi.org/10.1145/3439706.3446881","url":null,"abstract":"Heterogeneous three-dimensional (3-D) package-level integration plays an increasingly important role in the design of higher functional density and lower power processors for general computing, machine learning and mobile applications. In TSMC's 3DFabricTM platform, the back end packaging technology Chip-on-Wafer-on-Substrate (CoWoS®) with the integration of High-Bandwidth Memory (HBM) has been successfully deployed in high performance compute and machine learning applications to achieve high compute throughput, while Integrated Fan-Out (InFO) packaging technology is widely used in mobile applications thanks to its small footprint. System on Integrated Chips (SoIC⃨), leveraging advanced front end Silicon process technology, offers an unprecedented bonding density for vertical stacking. Combining SoIC with CoWoS and InFO, the 3DFabric family of technologies provides a versatile and flexible platform for system design innovations. A 3DFabric design starts with system partitioning to decompose it into different functional components. In contrast to a monolithic design approach, these functional components can potentially be implemented in different technologies to optimize system performance, power, area, and cost. Then these component chips are re-integrated with 3DFabric advanced packaging technologies to form the system. There are new design challenges and opportunities arising from 3DFabric. To unleash its full potential and accelerate the product development, physical design solutions are developed. In this presentation, we will first review these advanced packaging technologies trends and design challenges. Then, we will present design solutions for 3-D chiplets and system integration.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128040821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Session details: Session 3: Advances in Placement 会议详情:会议3:就业进展

Proceedings of the 2021 International Symposium on Physical Design Pub Date : 2021-03-22 DOI: 10.1145/3457128

J. Shinnerl

引用次数: 0