{"title":"碳纳米管技术的进展:从晶体管到RISC-V微处理器","authors":"G. Hills","doi":"10.1145/3439706.3446897","DOIUrl":null,"url":null,"abstract":"Carbon nanotube (CNT) field-effect transistors (CNFETs) promise to improve the energy efficiency of very-large-scale integrated (VLSI) systems. However, multiple challenges have prevented VLSI CNFET circuits from being realized, including inherent nano-scale material defects, robust processing for yielding complementary CNFETs (i.e., CNT CMOS: including both PMOS and NMOS CNFETs), and major CNT variations. In this talk, we summarize techniques that we have recently developed to overcome these outstanding challenges, enabling VLSI CNFET circuits to be experimentally realized today using standard VLSI processing and design flows. Leveraging these techniques, we demonstrate the most complex CNFET circuits and systems to-date, including a three-dimensional (3D) imaging system comprising CNFETs fabricated directly on top of a silicon imager, CNT CMOS analog and mixed-signal circuits, 1 kilobit CNFET static random-access memory (SRAM) memory arrays, and a 16-bit RISC-V microprocessor built entirely out of CNFETs.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Advances in Carbon Nanotube Technologies: From Transistors to a RISC-V Microprocessor\",\"authors\":\"G. Hills\",\"doi\":\"10.1145/3439706.3446897\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Carbon nanotube (CNT) field-effect transistors (CNFETs) promise to improve the energy efficiency of very-large-scale integrated (VLSI) systems. However, multiple challenges have prevented VLSI CNFET circuits from being realized, including inherent nano-scale material defects, robust processing for yielding complementary CNFETs (i.e., CNT CMOS: including both PMOS and NMOS CNFETs), and major CNT variations. In this talk, we summarize techniques that we have recently developed to overcome these outstanding challenges, enabling VLSI CNFET circuits to be experimentally realized today using standard VLSI processing and design flows. Leveraging these techniques, we demonstrate the most complex CNFET circuits and systems to-date, including a three-dimensional (3D) imaging system comprising CNFETs fabricated directly on top of a silicon imager, CNT CMOS analog and mixed-signal circuits, 1 kilobit CNFET static random-access memory (SRAM) memory arrays, and a 16-bit RISC-V microprocessor built entirely out of CNFETs.\",\"PeriodicalId\":184050,\"journal\":{\"name\":\"Proceedings of the 2021 International Symposium on Physical Design\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-03-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2021 International Symposium on Physical Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/3439706.3446897\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2021 International Symposium on Physical Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/3439706.3446897","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Advances in Carbon Nanotube Technologies: From Transistors to a RISC-V Microprocessor
Carbon nanotube (CNT) field-effect transistors (CNFETs) promise to improve the energy efficiency of very-large-scale integrated (VLSI) systems. However, multiple challenges have prevented VLSI CNFET circuits from being realized, including inherent nano-scale material defects, robust processing for yielding complementary CNFETs (i.e., CNT CMOS: including both PMOS and NMOS CNFETs), and major CNT variations. In this talk, we summarize techniques that we have recently developed to overcome these outstanding challenges, enabling VLSI CNFET circuits to be experimentally realized today using standard VLSI processing and design flows. Leveraging these techniques, we demonstrate the most complex CNFET circuits and systems to-date, including a three-dimensional (3D) imaging system comprising CNFETs fabricated directly on top of a silicon imager, CNT CMOS analog and mixed-signal circuits, 1 kilobit CNFET static random-access memory (SRAM) memory arrays, and a 16-bit RISC-V microprocessor built entirely out of CNFETs.