{"title":"基于ml的单片三维集成电路导线RC预测及其在全芯片优化中的应用","authors":"S. Pentapati, B. W. Ku, S. Lim","doi":"10.1145/3439706.3447266","DOIUrl":null,"url":null,"abstract":"The state-of-the-art Monolithic 3D (M3D) IC design methodologies~\\citem3d:Ku-tcad-Compact2D, m3d:Panth-tcad-Shrunk2D use commercial electronic design automation tools built for 2D ICs to implement a pseudo-3D design and split it into two dies that are routed independently to create an M3D design. Therefore, an accurate estimation of 3D wire parasitics at the pseudo-3D stage is important to achieve a well optimized M3D design. In this paper, we present a regression model based on boosted decision tree learning to better predict the 3D wire parasitics (RCs) at the pseudo-3D stage. Our model is trained using individual net features as well as the full-chip design metrics using multiple instantiations of 8 different netlists and is tested on 3 unseen netlists. Compared to the Compact-2D~\\citem3d:Ku-tcad-Compact2D flow on its own as the reference pseudo-3D, the addition of our predictive model achieves up to $2.9 \\times$ and $1.7 \\times$ smaller root mean square error in the resistance and capacitance predictions respectively. On an unseen netlist design, we observe that our model provides 98.6% and 94.6% RC prediction accuracy in 3D and up to $6.4 \\times$ smaller total negative slack of the design compared to the result of Compact-2D flow resulting in a more timing-robust M3D IC. This model is not limited to Compact-2D, and can be extended to other pseudo-3D flows.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"ML-Based Wire RC Prediction in Monolithic 3D ICs with an Application to Full-Chip Optimization\",\"authors\":\"S. Pentapati, B. W. Ku, S. Lim\",\"doi\":\"10.1145/3439706.3447266\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The state-of-the-art Monolithic 3D (M3D) IC design methodologies~\\\\citem3d:Ku-tcad-Compact2D, m3d:Panth-tcad-Shrunk2D use commercial electronic design automation tools built for 2D ICs to implement a pseudo-3D design and split it into two dies that are routed independently to create an M3D design. Therefore, an accurate estimation of 3D wire parasitics at the pseudo-3D stage is important to achieve a well optimized M3D design. In this paper, we present a regression model based on boosted decision tree learning to better predict the 3D wire parasitics (RCs) at the pseudo-3D stage. Our model is trained using individual net features as well as the full-chip design metrics using multiple instantiations of 8 different netlists and is tested on 3 unseen netlists. Compared to the Compact-2D~\\\\citem3d:Ku-tcad-Compact2D flow on its own as the reference pseudo-3D, the addition of our predictive model achieves up to $2.9 \\\\times$ and $1.7 \\\\times$ smaller root mean square error in the resistance and capacitance predictions respectively. On an unseen netlist design, we observe that our model provides 98.6% and 94.6% RC prediction accuracy in 3D and up to $6.4 \\\\times$ smaller total negative slack of the design compared to the result of Compact-2D flow resulting in a more timing-robust M3D IC. This model is not limited to Compact-2D, and can be extended to other pseudo-3D flows.\",\"PeriodicalId\":184050,\"journal\":{\"name\":\"Proceedings of the 2021 International Symposium on Physical Design\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-03-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2021 International Symposium on Physical Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/3439706.3447266\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2021 International Symposium on Physical Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/3439706.3447266","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
ML-Based Wire RC Prediction in Monolithic 3D ICs with an Application to Full-Chip Optimization
The state-of-the-art Monolithic 3D (M3D) IC design methodologies~\citem3d:Ku-tcad-Compact2D, m3d:Panth-tcad-Shrunk2D use commercial electronic design automation tools built for 2D ICs to implement a pseudo-3D design and split it into two dies that are routed independently to create an M3D design. Therefore, an accurate estimation of 3D wire parasitics at the pseudo-3D stage is important to achieve a well optimized M3D design. In this paper, we present a regression model based on boosted decision tree learning to better predict the 3D wire parasitics (RCs) at the pseudo-3D stage. Our model is trained using individual net features as well as the full-chip design metrics using multiple instantiations of 8 different netlists and is tested on 3 unseen netlists. Compared to the Compact-2D~\citem3d:Ku-tcad-Compact2D flow on its own as the reference pseudo-3D, the addition of our predictive model achieves up to $2.9 \times$ and $1.7 \times$ smaller root mean square error in the resistance and capacitance predictions respectively. On an unseen netlist design, we observe that our model provides 98.6% and 94.6% RC prediction accuracy in 3D and up to $6.4 \times$ smaller total negative slack of the design compared to the result of Compact-2D flow resulting in a more timing-robust M3D IC. This model is not limited to Compact-2D, and can be extended to other pseudo-3D flows.