Snap-3D:面对面键合3D集成电路的受限位置驱动物理设计方法

Pruek Vanna-Iampikul, Chengjia Shao, Yi-Chen Lu, S. Pentapati, S. Lim
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引用次数: 9

摘要

3D集成技术是一个领先的选择,可以推动摩尔定律超越传统的缩放。由于缺乏商用3D研磨机和路由器,现有的3D物理设计流程严重依赖2D商业工具来处理3D IC物理合成。具体来说,这些流程首先构建2D设计,然后将其转换为3D设计。然而,一些作品表明,在这种2D-3D转换过程中,设计质量会下降。在本文中,我们用我们的Snap-3D克服了这个问题,这是一种构建商业质量3D ic的约束驱动放置方法。我们的主要想法是基于观察,如果标准单元高度被压缩一半并划分成多层,任何商业2D砂矿机都可以将它们放置在行结构上,自然实现高质量的3D放置。该方法可同时优化不同层的功率、性能和面积(PPA)指标,并将上述设计质量损失降至最低。7个工业设计的实验结果表明,与最先进的3D设计流程相比,Snap-3D实现了高达5.4%的带宽,10.1%的功率和92.3%的总负松弛改进。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Snap-3D: A Constrained Placement-Driven Physical Design Methodology for Face-to-Face-Bonded 3D ICs
3D integration technology is one of the leading options that can advance Moore's Law beyond conventional scaling. Due to the absence of commercial 3D placers and routers, existing 3D physical design flows rely heavily on 2D commercial tools to handle 3D IC physical synthesis. Specifically, these flows build 2D designs first and then convert them into 3D designs. However, several works demonstrate that design qualities degrade during this 2D-3D transformation. In this paper, we overcome this issue with our Snap-3D, a constraint-driven placement approach to build commercial-quality 3D ICs. Our key idea is based on the observation that if the standard cell height is contracted by one half and partitioned into multiple tiers, any commercial 2D placer can place them onto the row structure and naturally achieve high-quality 3D placement. This methodology is shown to optimize power, performance, and area (PPA) metrics across different tiers simultaneously and minimize the aforementioned design quality loss. Experimental results on 7 industrial designs demonstrate that Snap-3D achieves up to 5.4% wirelength, 10.1% power, and 92.3% total negative slack improvements compared with state-of-the-art 3D design flows.
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