2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)最新文献

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Analysis of Discharge Parameters Influenced by Electrode Velocity Based on LSTM Prediction Model 基于LSTM预测模型的电极速度对放电参数影响分析
X. He, Fangming Ruan, Lan Yin, Yanli Chen, Yaru Yang, Xiao Wang
{"title":"Analysis of Discharge Parameters Influenced by Electrode Velocity Based on LSTM Prediction Model","authors":"X. He, Fangming Ruan, Lan Yin, Yanli Chen, Yaru Yang, Xiao Wang","doi":"10.1109/ASID56930.2022.9995944","DOIUrl":"https://doi.org/10.1109/ASID56930.2022.9995944","url":null,"abstract":"Relationships were discussed in this work between discharge current and electrode moving speed, ionization coefficient, field strength, gas pressure, temperature, humidity and other factors. Gas flow distribution around electrode, according to Bernoulli's law in aerodynamics, was analyzed during the electrode moving toward the target. Mechanism was explained on forming of local part low vacuum in the discharge gap. Two sub-processes of gas ionization avalanche process and surface electronic emission process were used to describe small gap discharge. With Paschen's law, analysis of influence was performed on discharge current by electrode moving speed toward the target. Experiments were conducted many times based on test platform of electrostatic discharge electrode moving speed effect, while experiment data were recorded. Long Short-Term Memory network (LSTM) model was used to train and learn experimental data, predicted peak value of discharge current at different electrode moving speeds and rise time. The experimental results show that there is a strong correlation between the electrode moving speed and the peak discharge current, while there is a certain correlation between the electrode moving speed and the current rise time, but it is relatively weak. The research results maybe have some reference significance for the proposal and formulation of non-contact electrostatic discharge standards.","PeriodicalId":183908,"journal":{"name":"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129517282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Optimized Method for Large-Scale Pre-Training in Symbolic Music 符号音乐大规模预训练的优化方法
Shike Liu, Hongguang Xu, Ke Xu
{"title":"An Optimized Method for Large-Scale Pre-Training in Symbolic Music","authors":"Shike Liu, Hongguang Xu, Ke Xu","doi":"10.1109/ASID56930.2022.9995766","DOIUrl":"https://doi.org/10.1109/ASID56930.2022.9995766","url":null,"abstract":"A better understanding of music can effectively improve the performance of music recommendation or generation. Although it has been confirmed that simply using the training method of the BERT model has strong ability in the field of symbolic music, the performance of BERT still has significant potential to be improved. In this paper, we mainly focus on the BERT model and propose a method to enhance its performance in the symbolic music domain. In order to mitigate the problem of information leakage between adjacent music tokens in pre-training, we propose a masking strategy that optimizes pre-training by corrupting data in a novel mechanism. Furthermore, the pre-training datasets used in our work cover both classical and popular music, which can provide a more comprehensive knowledge of different sorts of music, where a dynamic masking strategy is also employed to make full use of the data. We evaluate our improved model on four downstream tasks, including the melody extraction, velocity prediction, composer classification, and emotion classification. Experiments demonstrate that our proposed method has better music understanding ability than the baselines.","PeriodicalId":183908,"journal":{"name":"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128991681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Intelligent Recognition of the Ultrasound Standard Plane of the Fetal Cranial Brain with the FCB-Net FCB-Net对胎儿颅脑超声标准平面的智能识别
Pang Zeng, Weifeng Yu, Zhonghua Liu, Yong Diao, Peizhong Liu
{"title":"Intelligent Recognition of the Ultrasound Standard Plane of the Fetal Cranial Brain with the FCB-Net","authors":"Pang Zeng, Weifeng Yu, Zhonghua Liu, Yong Diao, Peizhong Liu","doi":"10.1109/ASID56930.2022.9996076","DOIUrl":"https://doi.org/10.1109/ASID56930.2022.9996076","url":null,"abstract":"Ultrasound images can be acquired in real-time and quickly, and also have the advantage of being low cost and no radiation. Currently, ultrasound is widely used in clinical diagnosis. With the development of ultrasound, it is slowly becoming an essential part of the imaging examinations in obstetrics. Fetal cranial ultrasound plays a vital role in assessing fetal growth and development, decreasing the rate of birth defects, monitoring pregnancy, and assessing clinical diagnosis. Due to its ability to visualize the internal structures of the fetal cranial brain in standard planes, fetal cranial ultrasound is also essential in screening for fetal structural abnormalities. However, the conventional approach relies primarily on the ultrasound doctor to do the work manually, which is a time-consuming and laborious process. This paper proposed a convolutional neural network, FCB-Net, for recognition of the ultrasound standard plane of the fetal cranial brain. There are 5361 fetal intracranial ultrasound images collected, and they were randomly divided into 4258 for model training and 1103 for testing the performance of the model. The experiments have shown that our proposed FCB-Net has the best recognition performance for the fetal cranial brain, and the accuracy of FCB-Net has reached 91.66%.","PeriodicalId":183908,"journal":{"name":"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114555662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A SPA Countermeasure for Hardware Implementation of SM2 Algorithm SM2算法硬件实现的SPA对策
Zhanzhan Chen, Liji Wu, Zhenhui Zhang, Dehang Xiao, Xiangmin Zhang, Yan Liu
{"title":"A SPA Countermeasure for Hardware Implementation of SM2 Algorithm","authors":"Zhanzhan Chen, Liji Wu, Zhenhui Zhang, Dehang Xiao, Xiangmin Zhang, Yan Liu","doi":"10.1109/ASID56930.2022.9995777","DOIUrl":"https://doi.org/10.1109/ASID56930.2022.9995777","url":null,"abstract":"SM2 algorithm is widely used in financial IC cards. It has the advantages of fast operation speed and short signature, but it may also contain security vulnerabilities. Attackers can crack the secret key via Simple Power Analysis (SPA), which is the inexpensive and extremely effective method, causing a great threat to the security of SM2 algorithm. In order to improve the safety of SM2 algorithm, this paper introduces atomic algorithm to implement point addition and point doubling operation, and proposes precomputed Non Adjacent Form (NAF) random window algorithm to achieve scalar multiplication. Based on experimental analysis with SAKURA-G FPGA board, the improved SM2 algorithm can resist successfully SPA. Compared with the original algorithm, the time of computation is reduced by 67.5%, and the number of slice registers has increased by less than 5%. The security and speed of SM2 algorithm has been significantly improved.","PeriodicalId":183908,"journal":{"name":"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129977807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance and Security Enhancement Solutions for Positron Emission Tomography Medical Hardware 正电子发射断层扫描医疗硬件的性能和安全性增强解决方案
Zhuoheng Ran, Haosen Yu
{"title":"Performance and Security Enhancement Solutions for Positron Emission Tomography Medical Hardware","authors":"Zhuoheng Ran, Haosen Yu","doi":"10.1109/ASID56930.2022.9995986","DOIUrl":"https://doi.org/10.1109/ASID56930.2022.9995986","url":null,"abstract":"Positron Emission Tomography (PET) is an emerging medical imaging methodology for diagnosing cancer. The optimization and security solutions surrounding this technology are essential issues in biomedical engineering. Low-resolution and unauthorized modification of medical images will affect clinical analysis and medical diagnostics. To improve image quality and security while minimizing its impact on medical hardware, this paper analyzes a highly integrated data acquisition approach based on Time-over-Threshold (ToT) and proposes a lightweight security solution based on Physically Unclonable Function (PUF) for PET scan medical hardware. Compared to existing applications, the time-based sampling method can provide very good image quality, and the proposed watermarking and encryption method based on PUF enables enhanced privacy protection with fewer hardware costs for PET medical imaging technology.","PeriodicalId":183908,"journal":{"name":"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130982204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and Implementation of Data Navigator for Heterogeneous Multi-Core System 异构多核系统数据导航器的设计与实现
Hu Ge, Y. Song, Duoli Zhang, Zhen-cheng Chen, Yan Ma
{"title":"Design and Implementation of Data Navigator for Heterogeneous Multi-Core System","authors":"Hu Ge, Y. Song, Duoli Zhang, Zhen-cheng Chen, Yan Ma","doi":"10.1109/ASID56930.2022.9995747","DOIUrl":"https://doi.org/10.1109/ASID56930.2022.9995747","url":null,"abstract":"For a multi-core system with multiple peripherals, the usual communication between cores and data transmission between cores and peripherals is single, and the data transfer cannot be planned, shaped, or congested-controlled. In this research, a Data Navigator that is used to manage data transport in a multi-core system is studied. The Data Navigator consists of two parts: Data Manager and Data Transfer Controller. When so many devices are requested to transmit data, the data manager uses a three-level priority adjustment technique, and the data transfer controller switches to DMA mode and uses the AXI bus to convey the data. The proposed architecture may provide equitable and efficient data transmission in a certain multi-core system environment, balance response speed, complete data shaping, and improve system performance overall, according to experimental results.","PeriodicalId":183908,"journal":{"name":"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128275106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Safe Deep Reinforcement Learning Based on Sample Value Evaluation 基于样本值评估的安全深度强化学习
Rongjun Ye, Hao Wang, Huan Li
{"title":"Safe Deep Reinforcement Learning Based on Sample Value Evaluation","authors":"Rongjun Ye, Hao Wang, Huan Li","doi":"10.1109/ASID56930.2022.9996075","DOIUrl":"https://doi.org/10.1109/ASID56930.2022.9996075","url":null,"abstract":"In recent years, deep reinforcement learning has combined the advantages of reinforcement learning and deep learning, and has made great progress in decision-making tasks. However, the training of deep reinforcement learning requires frequent interactions between the agent and the environment and repeated experiments. Adversaries have chances to poison the sample data collected by the agent by attacking the experimental environment in the training process, thereby bringing security risks and serious consequences to the training process of reinforcement learning. This work is committed to addressing the security risks in the field of deep reinforcement learning. However, this work improves the algorithm from the perspective of sample data filtering, and improves the security performance of deep reinforcement learning algorithm. There are two contributions in this work: one is to defend against adversarial attacks against deep reinforcement learning through cluster analysis and sample value evaluation; the other is to propose a deep reinforcement learning algorithm based on sample value evaluation on the basis of deterministic strategy gradient algorithm. The algorithm uses the clustering method to classify the sample pool, and measures the contribution value and security risk of the sample to the model training through the sample value evaluation. The classic game experiments show that the proposed algorithm is safe and effective. It reduces the threat of the agent falling into the adversarial sample attack and improves the training performance of deep reinforcement learning.","PeriodicalId":183908,"journal":{"name":"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126596741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Floating-Point Unit Architecture Based on SweRV EH1 Core 基于SweRV EH1内核的浮点单元体系结构
Zhen Lei, Fan Cai, Jianyang Zhou, Zichao Guo
{"title":"A Floating-Point Unit Architecture Based on SweRV EH1 Core","authors":"Zhen Lei, Fan Cai, Jianyang Zhou, Zichao Guo","doi":"10.1109/ASID56930.2022.9995796","DOIUrl":"https://doi.org/10.1109/ASID56930.2022.9995796","url":null,"abstract":"Complex software programs place higher demands on processors' floating-point performance. As a promising and open-source Instruction Set Architecture (ISA), RISC-V can be extended to meet a wide range of requirements. In this paper, we design a tightly-coupled Floating-Point Unit (FPU) based on a RISC-V processor SweRV EH1 core. This FPU supports RV32F instruction set. Both simulation and FPGA prototype were built to verify it. It ran 4.5x faster than the original core, with a Whetstone benchmark score of 1.13 MWIPS/MHz. We also did logic synthesis using TSMC 90nm process library. It shows that the whole design can run at a maximum frequency of 350 MHz, and the area of this FPU is about 27.5 kGE.","PeriodicalId":183908,"journal":{"name":"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114201897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Improved SAMP Channel Estimation Method via Compressed Sensing for MIMO-OFDM Systems 一种基于压缩感知的MIMO-OFDM系统SAMP信道估计方法
Weiqiang Chen, Mingjie Zhuang
{"title":"An Improved SAMP Channel Estimation Method via Compressed Sensing for MIMO-OFDM Systems","authors":"Weiqiang Chen, Mingjie Zhuang","doi":"10.1109/ASID56930.2022.9995751","DOIUrl":"https://doi.org/10.1109/ASID56930.2022.9995751","url":null,"abstract":"To address the problem that in the Multiple-Input Multiple-Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) system, the Compressed Sensing (CS) greedy algorithm uses the inner product criterion in the process of selecting atoms for channel estimation will lose part of the original signal information and affect the accuracy of reconstruction, this paper uses the Dice criterion instead of the inner product criterion for atom screening, the Dice criterion can better preserve the original state of the atoms. Due to the problem that the fixed step size of the Sparsity Adaptive Matching Pursuit (SAMP) algorithm affects the accuracy of channel estimation, this paper proposes an improved SAMP algorithm by using the idea of power function variable step size. The simulation results show that the improved SAMP algorithm has better Mean Square Error (MSE) and Bit Error Rate (BER) estimation performance than the traditional compressed sensing greedy algorithm in MIMO-OFDM system.","PeriodicalId":183908,"journal":{"name":"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128039555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of 64-Bit High-Performance Embedded Processor Supporting RISC-V B-Extension 支持RISC-V b扩展的64位高性能嵌入式处理器设计
Ziqin Meng, Yunrui Zhang, Jianyang Zhou, Zichao Guo
{"title":"Design of 64-Bit High-Performance Embedded Processor Supporting RISC-V B-Extension","authors":"Ziqin Meng, Yunrui Zhang, Jianyang Zhou, Zichao Guo","doi":"10.1109/ASID56930.2022.9995771","DOIUrl":"https://doi.org/10.1109/ASID56930.2022.9995771","url":null,"abstract":"With the continuous development of IoT technology, edge computing and high-performance computing are being merged. Compared with 32-bit processors, 64-bit processors have obvious advantages in processing some large data sets and high-precision numerical computing tasks. At the same time, as an open-source instruction set, RISC-V has highly concise instruction coding and flexible modular expansion, which is very suitable for the implementation of embedded processors. In this paper, we refer to the micro-architecture of the open-source 32-bit RISC-V processor SweRV EH1 and design a 64-bit embedded processor that supports the RV64IMCB instruction set. We adopt the instruction set self-checking test scheme based on riscv-tests to complete the functional verification of the processor and carry out the FPGA prototype verification on the Xilinx KC705 hardware platform. Compared with the 32-bit SweRV EH1, the Dhrystone performance improved by 32.3% on 64-bit processors with B-extension. The experiment shows that implementing the B-extension in a 64-bit processor can bring a 28.8% increase in Dhrystone performance and an 11.8% increase in CoreMark performance with an additional area overhead of 8.4%.","PeriodicalId":183908,"journal":{"name":"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115314102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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