{"title":"A High Input Impedance Low Noise Analog Front-End Chip for Neural Signal Applications","authors":"Fan Wu, Yanping Ji, Wensi Wang","doi":"10.1109/ASID56930.2022.9995938","DOIUrl":"https://doi.org/10.1109/ASID56930.2022.9995938","url":null,"abstract":"A Capacitive Feedback Programmable Gain Instrumentation Amplifier (CFPGA) with input impedance boosting technique is proposed. Compared with traditional methods, the proposed negative capacitance programmable circuit can achieve higher input impedance without injecting current into human biopotential electrodes. Simulation results using TSMC's 180 nm CMOS technology show that the proposed input impedance boosting technique can achieve an input impedance higher than 1G. In addition, CFPGA can achieve 1–128 times of 7bit gain adjustable. The entire CFPGA achieves an input-equivalent noise density equal to $mathbf{29} mathbf{nV}/sqrt{mathbf{Hz}}$ at a supply voltage of 1.8V.","PeriodicalId":183908,"journal":{"name":"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126874426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Energy Efficient Edge Computing for Smart Applications in the Post-Moore Era","authors":"Y. Ha","doi":"10.1109/asid56930.2022.9995806","DOIUrl":"https://doi.org/10.1109/asid56930.2022.9995806","url":null,"abstract":"","PeriodicalId":183908,"journal":{"name":"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"356 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132830914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Classification of Analog Circuits Based on Graph Convolution Network","authors":"Zhiwei Zheng, Xiongbo Zhang, Yuefan Wang, Shan He, Chao Huang, Lin Li, Donghui Guo","doi":"10.1109/ASID56930.2022.9996007","DOIUrl":"https://doi.org/10.1109/ASID56930.2022.9996007","url":null,"abstract":"The determination of circuit type is an important prerequisite for automatic design of analog circuits. However, the same type of circuit will have some variants due to different design requirements or designers. In this paper, a graph convolution network framework used for analog circuit classification is proposed, which can effectively identify circuits and their variants. First, we convert the analog circuit netlist into the data of graph structure, and the circuit information is represented by features. By converting the data of graph structure into Fourier domain, we can convolute the circuit graph and propagate it linearly, and extract the characteristics of the circuit to identify the circuit type. We performed experiments on the data set of analog circuits, and the experimental results showed that the proposed graph convolutional network based method achieved the promising performance in identifying types of circuits and their variants.","PeriodicalId":183908,"journal":{"name":"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126504116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automatic recognition of fetal facial ultrasound standard planes based on improved YOLOv4","authors":"Hao Xue, Zhonghua Liu, Weifeng Yu, Peizhong Liu","doi":"10.1109/ASID56930.2022.9995820","DOIUrl":"https://doi.org/10.1109/ASID56930.2022.9995820","url":null,"abstract":"Accurate acquisition of standard planes of fetal facial ultrasound is essential for subsequent biometry and disease diagnosis. Foreign scholars have extensively researched algorithms for the automatic acquisition of ultrasound standard planes. We view standard plane identification as a detection task, unlike previous classification studies. This study proposes a lightweight target detection network for identifying fetal facial ultrasound standard planes. Methods: Firstly, the model is based on the YOLOv4 algorithm, and given the storage resource limitations of the ultrasound device, we used a lightweight network (GhostNet) to replace the YOLOv4 backbone feature extraction network (CSPDarkNet53). Results: The experimental results show that the average accuracy of the improved YOLOv4 algorithm is 98.06%. The model size is 42.7 MB, a reduction of 85% compared to the original YOLOv4. It takes only 0.07 seconds to detect an ultrasound image, which can fully meet the real-time clinical requirements. It has high detection speed and accuracy, and the model's size is reduced substantially. The algorithm can assist young ultrasonographers in better acquiring high-quality ultrasound images and, to some extent, can address the limitations of the traditional manual approach to acquiring standard planes.","PeriodicalId":183908,"journal":{"name":"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"556 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127074999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automated DDoS Attack Mitigation for Software Defined Network","authors":"Danni Wang, Sizhao Li","doi":"10.1109/ASID56930.2022.9996013","DOIUrl":"https://doi.org/10.1109/ASID56930.2022.9996013","url":null,"abstract":"Network security is a prominent topic that is gaining international attention. Distributed Denial of Service (DDoS) attack is often regarded as one of the most serious threats to network security. Software Defined Network (SDN) decouples the control plane from the data plane, which can meet various network requirements. But SDN can also become the object of DDoS attacks. This paper proposes an automated DDoS attack mitigation method that is based on the programmability of the Ryu controller and the features of the OpenFlow switch flow tables. The Mininet platform is used to simulate the whole process, from SDN traffic generation to using a K-Nearest Neighbor model for traffic classification, as well as identifying and mitigating DDoS attack. The packet counts of the victim's malicious traffic input port are significantly lower after the mitigation method is implemented than before the mitigation operation. The purpose of mitigating DDoS attack is successfully achieved.","PeriodicalId":183908,"journal":{"name":"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115329531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jiajing Li, Lixin Yang, Xi Feng, Y. Xing, Zhijie Chen, Peiyuan Wan
{"title":"UART Controller with FIFO Buffer Function Based on APB Bus","authors":"Jiajing Li, Lixin Yang, Xi Feng, Y. Xing, Zhijie Chen, Peiyuan Wan","doi":"10.1109/ASID56930.2022.9996035","DOIUrl":"https://doi.org/10.1109/ASID56930.2022.9996035","url":null,"abstract":"This paper proposes a UART communication interface based on APB bus with asynchronous FIFO buffer. Based on this design, the UART controller can be flexibly configured through the AMBA bus to support baud rate modification, transmission bits, configurability of parity mode and other functions. And the asynchronous FIFO buffer function is added for communication between high-speed devices and low-speed UART devices. During data transmission, the FIFO can buffer the data and the situation that the UART device occupies the APB bus and the processor for a long time can be avoided, improving the data transmission efficiency. The design is based on the UART transmission protocol. the finite state machine method is used to control the the transmission timing of UART interface, and RTL simulation and FPGA verification are carried out, showing good flexibility of this design.","PeriodicalId":183908,"journal":{"name":"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116014492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}