{"title":"支持RISC-V b扩展的64位高性能嵌入式处理器设计","authors":"Ziqin Meng, Yunrui Zhang, Jianyang Zhou, Zichao Guo","doi":"10.1109/ASID56930.2022.9995771","DOIUrl":null,"url":null,"abstract":"With the continuous development of IoT technology, edge computing and high-performance computing are being merged. Compared with 32-bit processors, 64-bit processors have obvious advantages in processing some large data sets and high-precision numerical computing tasks. At the same time, as an open-source instruction set, RISC-V has highly concise instruction coding and flexible modular expansion, which is very suitable for the implementation of embedded processors. In this paper, we refer to the micro-architecture of the open-source 32-bit RISC-V processor SweRV EH1 and design a 64-bit embedded processor that supports the RV64IMCB instruction set. We adopt the instruction set self-checking test scheme based on riscv-tests to complete the functional verification of the processor and carry out the FPGA prototype verification on the Xilinx KC705 hardware platform. Compared with the 32-bit SweRV EH1, the Dhrystone performance improved by 32.3% on 64-bit processors with B-extension. The experiment shows that implementing the B-extension in a 64-bit processor can bring a 28.8% increase in Dhrystone performance and an 11.8% increase in CoreMark performance with an additional area overhead of 8.4%.","PeriodicalId":183908,"journal":{"name":"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Design of 64-Bit High-Performance Embedded Processor Supporting RISC-V B-Extension\",\"authors\":\"Ziqin Meng, Yunrui Zhang, Jianyang Zhou, Zichao Guo\",\"doi\":\"10.1109/ASID56930.2022.9995771\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With the continuous development of IoT technology, edge computing and high-performance computing are being merged. Compared with 32-bit processors, 64-bit processors have obvious advantages in processing some large data sets and high-precision numerical computing tasks. At the same time, as an open-source instruction set, RISC-V has highly concise instruction coding and flexible modular expansion, which is very suitable for the implementation of embedded processors. In this paper, we refer to the micro-architecture of the open-source 32-bit RISC-V processor SweRV EH1 and design a 64-bit embedded processor that supports the RV64IMCB instruction set. We adopt the instruction set self-checking test scheme based on riscv-tests to complete the functional verification of the processor and carry out the FPGA prototype verification on the Xilinx KC705 hardware platform. Compared with the 32-bit SweRV EH1, the Dhrystone performance improved by 32.3% on 64-bit processors with B-extension. The experiment shows that implementing the B-extension in a 64-bit processor can bring a 28.8% increase in Dhrystone performance and an 11.8% increase in CoreMark performance with an additional area overhead of 8.4%.\",\"PeriodicalId\":183908,\"journal\":{\"name\":\"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)\",\"volume\":\"95 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-12-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASID56930.2022.9995771\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASID56930.2022.9995771","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of 64-Bit High-Performance Embedded Processor Supporting RISC-V B-Extension
With the continuous development of IoT technology, edge computing and high-performance computing are being merged. Compared with 32-bit processors, 64-bit processors have obvious advantages in processing some large data sets and high-precision numerical computing tasks. At the same time, as an open-source instruction set, RISC-V has highly concise instruction coding and flexible modular expansion, which is very suitable for the implementation of embedded processors. In this paper, we refer to the micro-architecture of the open-source 32-bit RISC-V processor SweRV EH1 and design a 64-bit embedded processor that supports the RV64IMCB instruction set. We adopt the instruction set self-checking test scheme based on riscv-tests to complete the functional verification of the processor and carry out the FPGA prototype verification on the Xilinx KC705 hardware platform. Compared with the 32-bit SweRV EH1, the Dhrystone performance improved by 32.3% on 64-bit processors with B-extension. The experiment shows that implementing the B-extension in a 64-bit processor can bring a 28.8% increase in Dhrystone performance and an 11.8% increase in CoreMark performance with an additional area overhead of 8.4%.