支持RISC-V b扩展的64位高性能嵌入式处理器设计

Ziqin Meng, Yunrui Zhang, Jianyang Zhou, Zichao Guo
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引用次数: 2

摘要

随着物联网技术的不断发展,边缘计算和高性能计算正在融合。与32位处理器相比,64位处理器在处理一些大型数据集和高精度数值计算任务方面具有明显的优势。同时,RISC-V作为一个开源指令集,具有高度简洁的指令编码和灵活的模块化扩展,非常适合嵌入式处理器的实现。本文参考开源32位RISC-V处理器SweRV EH1的微架构,设计了一款支持RV64IMCB指令集的64位嵌入式处理器。我们采用基于riscv-tests的指令集自检测试方案,完成处理器的功能验证,并在Xilinx KC705硬件平台上进行FPGA原型验证。与32位的SweRV EH1相比,Dhrystone在64位的b扩展处理器上的性能提高了32.3%。实验表明,在64位处理器上实现b扩展可以使Dhrystone性能提高28.8%,CoreMark性能提高11.8%,额外的面积开销为8.4%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of 64-Bit High-Performance Embedded Processor Supporting RISC-V B-Extension
With the continuous development of IoT technology, edge computing and high-performance computing are being merged. Compared with 32-bit processors, 64-bit processors have obvious advantages in processing some large data sets and high-precision numerical computing tasks. At the same time, as an open-source instruction set, RISC-V has highly concise instruction coding and flexible modular expansion, which is very suitable for the implementation of embedded processors. In this paper, we refer to the micro-architecture of the open-source 32-bit RISC-V processor SweRV EH1 and design a 64-bit embedded processor that supports the RV64IMCB instruction set. We adopt the instruction set self-checking test scheme based on riscv-tests to complete the functional verification of the processor and carry out the FPGA prototype verification on the Xilinx KC705 hardware platform. Compared with the 32-bit SweRV EH1, the Dhrystone performance improved by 32.3% on 64-bit processors with B-extension. The experiment shows that implementing the B-extension in a 64-bit processor can bring a 28.8% increase in Dhrystone performance and an 11.8% increase in CoreMark performance with an additional area overhead of 8.4%.
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