A Floating-Point Unit Architecture Based on SweRV EH1 Core

Abstract

Complex software programs place higher demands on processors' floating-point performance. As a promising and open-source Instruction Set Architecture (ISA), RISC-V can be extended to meet a wide range of requirements. In this paper, we design a tightly-coupled Floating-Point Unit (FPU) based on a RISC-V processor SweRV EH1 core. This FPU supports RV32F instruction set. Both simulation and FPGA prototype were built to verify it. It ran 4.5x faster than the original core, with a Whetstone benchmark score of 1.13 MWIPS/MHz. We also did logic synthesis using TSMC 90nm process library. It shows that the whole design can run at a maximum frequency of 350 MHz, and the area of this FPU is about 27.5 kGE.