ACM Trans. Embed. Comput. Syst.最新文献_第7页

Flexible filters in stream programs 流程序中的灵活过滤器

ACM Trans. Embed. Comput. Syst. Pub Date : 2013-12-01 DOI: 10.1145/2539036.2539041

R. Collins, L. Carloni

引用次数: 0

Analyzing an embedded sensor with timed automata in uppaal 一种具有时间自动机的嵌入式传感器在upal中的应用

ACM Trans. Embed. Comput. Syst. Pub Date : 2013-12-01 DOI: 10.1145/2539036.2539040

T. Bourke, A. Sowmya

{"title":"Analyzing an embedded sensor with timed automata in uppaal","authors":"T. Bourke, A. Sowmya","doi":"10.1145/2539036.2539040","DOIUrl":"https://doi.org/10.1145/2539036.2539040","url":null,"abstract":"An infrared sensor is modeled and analyzed in Uppaal. The sensor typifies the sort of component that engineers regularly integrate into larger systems by writing interface hardware and software.\u0000 In all, three main models are developed. In the first model, the timing diagram of the sensor is interpreted and modeled as a timed safety automaton. This model serves as a specification for the complete system. A second model that emphasizes the separate roles of driver and sensor is then developed. It is validated against the timing diagram model using an existing construction that permits the verification of timed trace inclusion, for certain models, by reachability analysis (i.e., model checking). A transmission correctness property is also stated by means of an auxiliary automaton and shown to be satisfied by the model.\u0000 A third model is created from an assembly language driver program, using a direct translation from the instruction set of a processor with simple timing behavior. This model is validated against the driver component of the second timing diagram model using the timed trace inclusion validation technique. The approach and its limitations offer insight into the nature and challenges of programming in real time.","PeriodicalId":183677,"journal":{"name":"ACM Trans. Embed. Comput. Syst.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126137991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A theory of robust omega-regular software synthesis 稳健的-规则软件合成理论

ACM Trans. Embed. Comput. Syst. Pub Date : 2013-12-01 DOI: 10.1145/2539036.2539044

R. Majumdar, Elaine Render, P. Tabuada

引用次数: 13

Dynamic profiling and fuzzy-logic-based optimization of sensor network platforms 传感器网络平台的动态分析与模糊逻辑优化

ACM Trans. Embed. Comput. Syst. Pub Date : 2013-12-01 DOI: 10.1145/2539036.2539047

A. Lizarraga, Roman L. Lysecky, Susan Lysecky, A. Gordon-Ross

{"title":"Dynamic profiling and fuzzy-logic-based optimization of sensor network platforms","authors":"A. Lizarraga, Roman L. Lysecky, Susan Lysecky, A. Gordon-Ross","doi":"10.1145/2539036.2539047","DOIUrl":"https://doi.org/10.1145/2539036.2539047","url":null,"abstract":"The commercialization of sensor-based platforms is facilitating the realization of numerous sensor network applications with diverse application requirements. However, sensor network platforms are becoming increasingly complex to design and optimize due to the multitude of interdependent parameters that must be considered. To further complicate matters, application experts oftentimes are not trained engineers, but rather biologists, teachers, or agriculturists who wish to utilize the sensor-based platforms for various domain-specific tasks. To assist both platform developers and application experts, we present a centralized dynamic profiling and optimization platform for sensor-based systems that enables application experts to rapidly optimize a sensor network for a particular application without requiring extensive knowledge of, and experience with, the underlying physical hardware platform. In this article, we present an optimization framework that allows developers to characterize application requirements through high-level design metrics and fuzzy-logic-based optimization. We further analyze the benefits of utilizing dynamic profiling information to eliminate the guesswork of creating a “good” benchmark, present several reoptimization evaluation algorithms used to detect if re-optimization is necessary, and highlight the benefits of the proposed dynamic optimization framework compared to static optimization alternatives.","PeriodicalId":183677,"journal":{"name":"ACM Trans. Embed. Comput. Syst.","volume":"486 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121349446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Throughput-memory footprint trade-off in synthesis of streaming software on embedded multiprocessors 嵌入式多处理器上流软件合成的吞吐量-内存占用权衡

ACM Trans. Embed. Comput. Syst. Pub Date : 2013-12-01 DOI: 10.1145/2539036.2539042

Matin Hashemi, Mohammad H. Foroozannejad, S. Ghiasi

引用次数: 8

Register allocation for embedded systems to simultaneously reduce energy and temperature on registers 嵌入式系统的寄存器分配，以同时减少寄存器上的能量和温度

ACM Trans. Embed. Comput. Syst. Pub Date : 2013-12-01 DOI: 10.1145/2539036.2539046

Tiantian Liu, A. Orailoglu, C. Xue, Minming Li

{"title":"Register allocation for embedded systems to simultaneously reduce energy and temperature on registers","authors":"Tiantian Liu, A. Orailoglu, C. Xue, Minming Li","doi":"10.1145/2539036.2539046","DOIUrl":"https://doi.org/10.1145/2539036.2539046","url":null,"abstract":"Energy and thermal issues are two important concerns for embedded system design. Diminished energy dissipation leads to a longer battery life, while reduced temperature hotspots decelerate the physical failure mechanisms. The instruction fetch logic associated with register access has a significant contribution towards the total energy consumption. Meanwhile, the register file has also been previously shown to exhibit the highest temperature compared to the rest of the components in an embedded processor. Therefore, the optimization of energy and the resolution of the thermal issue for register accesses are of great significance. In this article, register allocation techniques are studied to simultaneously reduce energy consumption and heat buildup on register accesses for embedded systems. Contrary to prevailing intuition, we observe that optimizing energy and optimizing temperature on register accesses conflict with each other. We introduce a rotator hardware in the instruction decoder to facilitate a balanced solution for the two conflicting objectives. Algorithms for register allocation and refinement are proposed based on the access patterns and the effects of the rotator. Experimental results show that the proposed algorithms obtain notable improvements of energy and peak temperature for embedded applications.","PeriodicalId":183677,"journal":{"name":"ACM Trans. Embed. Comput. Syst.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126174121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A regression test selection technique for embedded software 嵌入式软件的回归测试选择技术

ACM Trans. Embed. Comput. Syst. Pub Date : 2013-12-01 DOI: 10.1145/2539036.2539043

Swarnendu Biswas, R. Mall, M. Satpathy

{"title":"A regression test selection technique for embedded software","authors":"Swarnendu Biswas, R. Mall, M. Satpathy","doi":"10.1145/2539036.2539043","DOIUrl":"https://doi.org/10.1145/2539036.2539043","url":null,"abstract":"The current approaches for regression test selection of embedded programs are usually based on data- and control-dependency analyses, often augmented with human reasoning. Existing techniques do not take into account additional execution dependencies which may exist among code elements in such programs due to features such as tasks, task deadlines, task precedences, and intertask communications. In this context, we propose a model-based regression test selection technique for such programs. Our technique first constructs a graph model of the program; the proposed graph model has been designed to capture several characteristics of embedded programs, such as task precedence order, priority, intertask communication, timers, exceptions and interrupt handlers, which we consider important for regression-test selection. Our regression test selection technique selects test cases based on an analysis of the constructed graph model. We have implemented our technique to realize a prototype tool. The experimental results obtained using this tool show that, on average, our approach selects about 28.33% more regression test cases than those selected by a traditional approach. We observed that, on average, 36.36% of the fault-revealing test cases were overlooked by the existing regression test selection technique.","PeriodicalId":183677,"journal":{"name":"ACM Trans. Embed. Comput. Syst.","volume":"792 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133108301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

The benefits of using variable-length pipelined operations in high-level synthesis 在高级合成中使用变长流水线操作的好处

ACM Trans. Embed. Comput. Syst. Pub Date : 2013-12-01 DOI: 10.1145/2539036.2539048

Y. Ben-Asher, Nadav Rotem

{"title":"The benefits of using variable-length pipelined operations in high-level synthesis","authors":"Y. Ben-Asher, Nadav Rotem","doi":"10.1145/2539036.2539048","DOIUrl":"https://doi.org/10.1145/2539036.2539048","url":null,"abstract":"Current high-level synthesis systems synthesize arithmetic units of a fixed known number of stages, and the scheduler mainly determines when units are activated. We focus on scheduling techniques for the high-level synthesis of pipelined arithmetic units where the number of stages of these operations is a free parameter of the synthesis. This problem is motivated by the ability to automatically create pipelined functional units, such as multipliers, with different pipe lengths. These units have different characteristics in terms of parallelism level, clock latency, frequency, etc. This article presents the Variable-length Pipeline Scheduler (VPS). The ability to synthesize variable-length pipelined units expands the known scheduling problem of high-level synthesis to include a search for a minimal number of hardware units (operations) and their desired number of stages. The proposed search procedure is based on algorithms that find a local minima in a d-dimensional grid, thus avoiding the need to evaluate all possible points in the space. We have implemented a C language compiler for VPS targeting FPGAs. Our results demonstrate that using variable-length pipeline units can reduce the overall resource usage and improve the execution time when synthesized onto an FPGA. The proposed search is sufficiently fast, taking only a few seconds, allowing an interactive mode of work. A comparison with xPilot shows a significant saving of hardware resources while maintaining comparable execution times of the resulting circuits. This work is an extension of a previous paper [Ben-Asher and Rotem 2008]","PeriodicalId":183677,"journal":{"name":"ACM Trans. Embed. Comput. Syst.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127426279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A hardware architecture for real-time object detection using depth and edge information 利用深度和边缘信息进行实时目标检测的硬件架构

ACM Trans. Embed. Comput. Syst. Pub Date : 2013-12-01 DOI: 10.1145/2539036.2539050

C. Kyrkou, Christos Ttofis, T. Theocharides

{"title":"A hardware architecture for real-time object detection using depth and edge information","authors":"C. Kyrkou, Christos Ttofis, T. Theocharides","doi":"10.1145/2539036.2539050","DOIUrl":"https://doi.org/10.1145/2539036.2539050","url":null,"abstract":"Emerging embedded 3D vision systems for robotics and security applications utilize object detection to perform video analysis in order to intelligently interact with their host environment and take appropriate actions. Such systems have high performance and high detection-accuracy demands, while requiring low energy consumption, especially when dealing with embedded mobile systems. However, there is a large image search space involved in object detection, primarily because of the different sizes in which an object may appear, which makes it difficult to meet these demands. Hence, it is possible to meet such constraints by reducing the search space involved in object detection. To this end, this article proposes a depth and edge accelerated search method and a dedicated hardware architecture that implements it to provide an efficient platform for generic real-time object detection. The hardware integration of depth and edge processing mechanisms, with a support vector machine classification core onto an FPGA platform, results in significant speed-ups and improved detection accuracy. The proposed architecture was evaluated using images of various sizes, with results indicating that the proposed architecture is capable of achieving real-time frame rates for a variety of image sizes (271 fps for 320 × 240, 42 fps for 640 × 480, and 23 fps for 800 × 600) compared to existing works, while reducing the false-positive rate by 52%.","PeriodicalId":183677,"journal":{"name":"ACM Trans. Embed. Comput. Syst.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125884310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Energy-aware code motion for GPU shader processors GPU着色器处理器的能量感知代码运动

ACM Trans. Embed. Comput. Syst. Pub Date : 2013-12-01 DOI: 10.1145/2539036.2539045

Yi-Ping You, Shengjue Wang

引用次数: 4