R. Martins, N. Lourenço, S. Rodrigues, J. Guilherme, N. Horta
{"title":"AIDA: Automated analog IC design flow from circuit level to layout","authors":"R. Martins, N. Lourenço, S. Rodrigues, J. Guilherme, N. Horta","doi":"10.1109/SMACD.2012.6339409","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339409","url":null,"abstract":"This paper presents AIDA, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to a physical layout description. AIDA results from the integration of two in-house tools, namely, GENOM-POF and LAYGEN II. GENOM-POF performs fully automated circuit-level synthesis implemented with a multi-objective multi-constraint optimization approach, which addresses robust design requirements by considering Corners analysis together with an electrical simulator as the evaluation engine. LAYGEN II implements a DRC proved fully automated layout generation based on a sized circuit-level description and high level layout guidelines, described in a technology independent abstract layout template. The expert knowledge is used by LAYGEN II to guide the evolutionary optimization kernels during the automatic layout generation. Moreover, evolutionary computation techniques are extensively used, at both circuit-level and physical-level, as tool to solve design optimization problems. Finally, AIDA environment is demonstrated for the IC design of a classical circuit-level topology and state-of-the-art technology, and validated by industrial simulators and analysis tools, such as, HSPICE® and CALIBRE®.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126546322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Short-circuit-path and floating-node verification of analog circuits in power-down mode","authors":"M. Zwerger, H. Graeb","doi":"10.1109/SMACD.2012.6339384","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339384","url":null,"abstract":"In this work, a method for aging-aware verification of analog circuits in power-down mode is presented. The core of the method is a voltage propagation algorithm that estimates node voltages based on circuit structure only. No numerical simulation is needed. This is crucial as simulation models are often unreliable in power-down mode. A precise graph-based formulation of the voltage propagation algorithm is given. Complexity analysis shows that the propagation algorithm has quadratic complexity. Experimental results show the efficacy and efficiency of the method.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126085769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Volterra series analysis of down-conversion CMOS mixer with high IIP2 and IIP3","authors":"M. Mollaalipour, H. M. Naimi","doi":"10.1109/SMACD.2012.6339452","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339452","url":null,"abstract":"In this paper a new highly linear CMOS mixer is proposed that utilizes simultaneously second and third-order distortion cancellation using second harmonic injection, and an in-depth analysis of the mixer is presented. Simulations in a 0.18 μm CMOS technology demonstrate that IIP3 and IIP2 of the proposed mixer have 10dB and 26dB improvements, respectively, compared with the conventional Gilbert-type mixer and the NF will not be degraded mainly. The mixer has a gain of 15 dB and 1.8V supply voltage, and current consumption is increased less than 1 mA in this technique.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123246334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}