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2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)最新文献

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Transient computation of DC-DC converters using a new envelope following method 一种新的包络跟踪法在DC-DC变换器暂态计算中的应用
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339381
A. Gheorghe, F. Constantinescu, M. Nitescu
{"title":"Transient computation of DC-DC converters using a new envelope following method","authors":"A. Gheorghe, F. Constantinescu, M. Nitescu","doi":"10.1109/SMACD.2012.6339381","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339381","url":null,"abstract":"A new envelope following algorithm, using both exponential and quadratic approximations of the envelope, is proposed. Using the most appropriate approximation for each state variable, this algorithm switches automatically between the methods of approximation. A new criterion for the efficiency of an envelope following analysis is proposed. In the case of two buck converters this analysis shortens the simulation time jumping over some switch signal periods and reaching finally the same steady state as the usual transient analysis. The proposed algorithm proves to be in this case the most efficient, followed by the algorithm implemented in SPECTRE RF and the algorithm implemented in PAN. This efficiency hierarchy is the same for all analyzed cases.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115040097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel software environment for design and simulation of piezoMEMS 一种新颖的设计与仿真软件环境
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339432
A. Cruau, G. Schropfer, G. Lorenz
{"title":"A novel software environment for design and simulation of piezoMEMS","authors":"A. Cruau, G. Schropfer, G. Lorenz","doi":"10.1109/SMACD.2012.6339432","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339432","url":null,"abstract":"This paper describes the use of a novel design and simulation platform for piezoMEMS devices and systems. This platform called MEMS+ is part of a complete environment where the seamless link to standard EDA and CAD tools enables complete and easy system simulation. The methodology is applied to two piezodevices examples, a unimorph cantilever energy harvester and a piston micromirror.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122083166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An integrated MEG acquisition system with CMOS instrumentation amplifier and offset cancellation 一种集成了CMOS仪表放大器和偏移抵消的MEG采集系统
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339422
HyunJune Lyu, Jae Sung Choi, Hyun Jin Choi, G. Park, S. Han, Jungryul Choi
{"title":"An integrated MEG acquisition system with CMOS instrumentation amplifier and offset cancellation","authors":"HyunJune Lyu, Jae Sung Choi, Hyun Jin Choi, G. Park, S. Han, Jungryul Choi","doi":"10.1109/SMACD.2012.6339422","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339422","url":null,"abstract":"We propose a CMOS-based Magnetoencephalography(MEG) acquisition system. The MEG acquisition system consists of a small-sized high inductance coil sensor and an instrumentation amplifier (IA). The small-sized high inductance coil sensor is fabricated in 0.18 μm standard CMOS process. Output signal sensitivity of MEG acquisition sensor chip is 3.25fT/μV and noise figure of 34.9fT/(√Hz). The IA is designed along with low-pass and high-pass filters to reduce noise. It draws only 540 μA from a standard 3.3V battery, making it suitable for use in portable systems. By using current feedback techniques it achieves a common mode rejection ratio of 120 dB while the total noise referred to input is kept below 0.87 μV.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116503673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Current density aware algorithm for net generation in analog high current application 模拟大电流应用中网络生成的电流密度感知算法
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339440
J. M. Jonqueres, J. Portal, G. Micolau, O. Ginez
{"title":"Current density aware algorithm for net generation in analog high current application","authors":"J. M. Jonqueres, J. Portal, G. Micolau, O. Ginez","doi":"10.1109/SMACD.2012.6339440","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339440","url":null,"abstract":"In deep submicron VLSI circuits, excessive current density in interconnects is a major concern for analog high current application. If current over maximum density is not effectively mitigated, this can lead to phenomena like electromigration, voltage drop and electrical overload. It is a hot topic of interest in modern circuits due to the decrease of metal track sizes while high currents are necessary in automotive or mobile applications. In this paper, an algorithm considering current constraints for net generation is presented. It determines all branch currents and proposes a routing for signal nets with current-dependent wire width. First, the phenomena of electromigration and voltage drop are introduced. The current constrained wire planning algorithm is presented and shows results improved on average by about 10% for area and almost 27% for CPU time compared with existing solution.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124356162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A high bandwidth 11-bit 1.5GS/s track and hold amplifier in 0.25 µm SiGe BiCMOS 高带宽11位1.5GS/s轨道和保持放大器在0.25µm SiGe BiCMOS
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339414
F. Cannone, D. Cascella, G. Avitabile, G. Coviello
{"title":"A high bandwidth 11-bit 1.5GS/s track and hold amplifier in 0.25 µm SiGe BiCMOS","authors":"F. Cannone, D. Cascella, G. Avitabile, G. Coviello","doi":"10.1109/SMACD.2012.6339414","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339414","url":null,"abstract":"The paper describes a Track and Hold Amplifier suitable for high-speed and high resolution applications like Software Defined Radios. Thanks to the adopted techniques to maximize the resolution without reducing the sampling frequency, all the non idealities limiting the equivalent number of bits have been taken into account. In particular a novel technique to reduce the third harmonic distortion has been proposed and exploited. Post-layout simulations show that the performances are quite constant and the linearity is compatible with 11-bit (SFDR) at Fs= 1.5GS/s up to a frequency 1GHz.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131264325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
PERL scripts-based netlist analysis tool for the detection of ESD “big buffer” configurations 基于PERL脚本的网表分析工具，用于检测ESD“大缓冲区”的配置
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339391
S. Darfeuille
{"title":"PERL scripts-based netlist analysis tool for the detection of ESD “big buffer” configurations","authors":"S. Darfeuille","doi":"10.1109/SMACD.2012.6339391","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339391","url":null,"abstract":"In this paper a tool written with the scripting language PERL and looking for “big buffer” configurations in analogue circuit designs is introduced. A big buffer is obtained when one or several big PMOS transistor (PMOST) and a small NMOS transistor (NMOST) are connected together while their gates are pulled-down to ground. During an electrostatic discharge (ESD) event this can result in the destruction of the NMOS device. Thus, it is crucial to prevent such configurations to be used in integrated circuits, especially considering the current trend to move towards advanced CMOS technology nodes even for analogue and RF design. The tool operates on Spectre netlists so it can be used even during very early phase of the circuit development process, enabling faster and simpler corrections at schematic level.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129951246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A fully automated design flow for planar inductors 平面电感器的全自动设计流程
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339447
R. Gonzalez-Echevarria, R. Castro-López, E. Roca, F. Fernández, J. López-Villegas, J. Sieiro
{"title":"A fully automated design flow for planar inductors","authors":"R. Gonzalez-Echevarria, R. Castro-López, E. Roca, F. Fernández, J. López-Villegas, J. Sieiro","doi":"10.1109/SMACD.2012.6339447","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339447","url":null,"abstract":"Integrated inductors performances are difficult to model due to the parasitic effects present at high frequencies. Typically, RF designers use electromagnetic simulation during the design flow to tune their circuits until all designs requirements are fulfilled or use the set of, not always conveniently tuned, inductors provided by the foundries. In this paper, a multi-objective optimization algorithm is combined with a full-wave electromagnetic evaluator to obtain a tool for synthesis of inductors with optimum performance trade-offs. The automation of layout generation and simulation tasks are described in details.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129008205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Modeling switching losses in MOSFETs half-bridges mosfet半桥开关损耗建模
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339425
G. Di Capua, N. Femia
{"title":"Modeling switching losses in MOSFETs half-bridges","authors":"G. Di Capua, N. Femia","doi":"10.1109/SMACD.2012.6339425","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339425","url":null,"abstract":"This paper discusses the modeling of switching losses in MOSFETs half-bridges. The model proposed in the paper provides a trade-off between accuracy and computing simplicity for quick feasibility investigations and comparative evaluations among different MOSFETs combinations to be selected for the design of high-efficiency switching power supplies. The proposed model also enables a detailed analysis of capacitive currents circulating through the MOSFETs during commutations, thus allowing a more accurate loss understanding and calculation.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121448327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Surrogate models of Pareto-optimal planar inductors 帕累托最优平面电感器的替代模型
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339412
M. Kotti, R. Gonzalez-Echevarria, E. Roca, R. Castro-López, F. Fernández, M. Fakhfakh, J. Sieiro, J. López-Villegas
{"title":"Surrogate models of Pareto-optimal planar inductors","authors":"M. Kotti, R. Gonzalez-Echevarria, E. Roca, R. Castro-López, F. Fernández, M. Fakhfakh, J. Sieiro, J. López-Villegas","doi":"10.1109/SMACD.2012.6339412","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339412","url":null,"abstract":"Systematic design methodologies for wireless transceivers require an efficient design of integrated inductors. Early availability of feasible trade-offs between inductance, quality factor and area, is a key enabler towards the improvement of such design methodologies. This paper introduces such an approach in two steps. First, a Pareto-optimal performance front of integrated inductors is obtained by embedding an electromagnetic simulator into a multi-objective optimization tool. Then, starting from the obtained optimal samples, a surrogate model of the performance front is obtained. Experimental results in a 0.35μm CMOS technology are provided.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125206108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Optimization of fully-integrated power converter circuits comprising tapered inductor layout and temperature effects 包含锥形电感布局和温度效应的全集成功率转换器电路的优化
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339411
P. Callemeyn, D. De Jonghe, G. Gielen, M. Steyaert
{"title":"Optimization of fully-integrated power converter circuits comprising tapered inductor layout and temperature effects","authors":"P. Callemeyn, D. De Jonghe, G. Gielen, M. Steyaert","doi":"10.1109/SMACD.2012.6339411","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339411","url":null,"abstract":"A technique for the optimization of fully-integrated inductive DC-DC converters is presented. An optimization framework is used to acquire an optimal converter, focusing on the on-chip inductor as well as on the accurate layout-based modeling of temperature effects. For the inductor in inductive DC-DC converters, a tapered topology is introduced. A fully-integrated DC-DC boost converter is designed and optimized in a 0.13 μm CMOS technology. The power loss in the circuit is reduced with 27 % resulting in a 7 % efficiency improvement, compared to a fully-integrated DC-DC boost converter with a regular inductor topology.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130571649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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