基于PERL脚本的网表分析工具,用于检测ESD“大缓冲区”的配置

S. Darfeuille
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引用次数: 2

摘要

本文介绍了一个用PERL编写的在模拟电路设计中寻找“大缓冲”组态的工具。当一个或几个大的PMOS晶体管(PMOST)和一个小的NMOS晶体管(最)连接在一起时,它们的栅极被拉到地,就可以得到一个大的缓冲器。在静电放电(ESD)事件中,这可能导致NMOS器件的破坏。因此,防止这种配置在集成电路中使用是至关重要的,特别是考虑到当前的趋势是向先进的CMOS技术节点移动,即使是模拟和射频设计。该工具在Spectre网表上运行,因此即使在电路开发过程的早期阶段也可以使用,从而在原理图级别实现更快,更简单的校正。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
PERL scripts-based netlist analysis tool for the detection of ESD “big buffer” configurations
In this paper a tool written with the scripting language PERL and looking for “big buffer” configurations in analogue circuit designs is introduced. A big buffer is obtained when one or several big PMOS transistor (PMOST) and a small NMOS transistor (NMOST) are connected together while their gates are pulled-down to ground. During an electrostatic discharge (ESD) event this can result in the destruction of the NMOS device. Thus, it is crucial to prevent such configurations to be used in integrated circuits, especially considering the current trend to move towards advanced CMOS technology nodes even for analogue and RF design. The tool operates on Spectre netlists so it can be used even during very early phase of the circuit development process, enabling faster and simpler corrections at schematic level.
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