2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)最新文献_第2页

Electromechanical performance comparison for different CMUT element geometries 不同CMUT元件几何形状的机电性能比较

2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339429

J. Mendoza-Lopez, C. Sánchez-López

引用次数: 7

Simple and accurate modeling of double-gate FinFET fin body variations 双栅FinFET翅片体变化的简单准确建模

2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339390

D. Kim, Yesung Kang, Youngmin Kim

引用次数: 5

SCALES - A behavioral simulator for pipelined analog-to-digital converter design 用于流水线模数转换器设计的行为模拟器

2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339439

C. Silva, N. Horta, J. Guilherme, P. Ayzac

引用次数: 2

Automatic inspection of SET sensitivity in analog cells 模拟单元的SET灵敏度自动检测

2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339394

F. Marquez, F. Muñoz, F. R. Palomo, M. Aguirre, M. Ullán

引用次数: 2

Determining the dominant nonlinear contributions in a multistage op-amp in a feedback configuration 确定反馈配置中多级运放的主要非线性贡献

2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339453

A. Cooman, E. Geerardyn, G. Vandersteen, Y. Rolain

引用次数: 4

Temperature sensor placement including routing overhead and sampling inaccuracies 温度传感器的放置，包括路由开销和采样误差

2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339419

P. Ituero, F. García-Redondo, M. López-Vallejo

引用次数: 4

A circuit synthesis technique based on network determinant expansion 基于网络行列式展开的电路综合技术

2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339397

V. Filaretov, K. Gorshkov, A. Mikheenko

引用次数: 10

A formal equivalence checking methodology for Simulink and Register Transfer Level designs 一个正式的等效检查方法，用于Simulink和寄存器传输级设计

2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339457

M. O. Saglamdemir, A. Sen, G. Dundar

{"title":"A formal equivalence checking methodology for Simulink and Register Transfer Level designs","authors":"M. O. Saglamdemir, A. Sen, G. Dundar","doi":"10.1109/SMACD.2012.6339457","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339457","url":null,"abstract":"Driven by the increase in complexity of design, time-to-market pressure and the need for a high level of collaboration between multiple discipline teams in a project, model based design has become the inevitable choice for IC Design projects. High-level models are being substantially used as the reference for implementation of the Register Transfer Level (RTL) counterpart of the designs. In that respect, Matlab/Simulink is one of the adopted high level modeling platforms in the IC design industry. However, checking the formal equivalence of the models with their RTL counterparts is still an area of interest to be investigated. In this study, a methodology addressing that matter is proposed. Simulink models of interest in this paper comprise built-in Simulink blocks, Stateflow blocks modeling the state machines, and user-defined blocks. Proposed methodology utilizes Simulink's Hardware Design Language (HDL) Coder and Real Time Workshop (RTW) tools, Mentor Graphics' Catapult, and Synopsys' Formality in the flow. Building of the methodology is explained with a simple example. Then the methodology is applied to multiple designs, including Advanced Encryption Standard (AES) to verify its applicability.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"29 18","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132089020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Hierarchical model-order reduction for robust design of parameter-varying systems 变参数系统鲁棒设计的层次模型阶数约简

2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339430

M. Hauser, C. Salzig

引用次数: 1

Variability aware support vector machine based macromodels for statistical estimation of subthreshold leakage power 基于可变性感知支持向量机的亚阈值泄漏功率统计估计宏模型

2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339387

L. Garg, V. Sahula

{"title":"Variability aware support vector machine based macromodels for statistical estimation of subthreshold leakage power","authors":"L. Garg, V. Sahula","doi":"10.1109/SMACD.2012.6339387","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339387","url":null,"abstract":"In this paper, we present an accurate and efficient stack based macromodel for statistical subthreshold leakage power characterization of cmos gates. Our methodology is based on first characterizing the leakage power of basic stacks and then estimating the subthreshold leakage power of gates based on these stacks. We develop support vector machine (SVM) based macromodels to characterize the transistor stacks of cmos gates, while accounting the combined effect of process variation in length (L), threshold voltage (Vth), oxide thickness (Tox), supply voltage (0.6v-1.2v), temperature (0°C-100°C) and width (45nm-200nm) scalable at the same time. Our experiments show that we only need 30 stack models to predict the subthreshold leakage power of 7 basic gates across 58 input combinations. SVM based models have the ability to predict the leakage power with maximum average error of less than 0.634% in mean for 4 input NOR gate and maximum average error of 1.952% in standard deviation for 3 input NOR gate. Our results also show that there is on the average 17× improvement in runtime for estimating the mean and standard deviation of leakage power of a gate with 5000 Monte Carlo simulations.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115499827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4