Short-circuit-path and floating-node verification of analog circuits in power-down mode

Abstract

In this work, a method for aging-aware verification of analog circuits in power-down mode is presented. The core of the method is a voltage propagation algorithm that estimates node voltages based on circuit structure only. No numerical simulation is needed. This is crucial as simulation models are often unreliable in power-down mode. A precise graph-based formulation of the voltage propagation algorithm is given. Complexity analysis shows that the propagation algorithm has quadratic complexity. Experimental results show the efficacy and efficiency of the method.