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Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)最新文献

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A test structure for characterization of CMOS APS 一种用于CMOS APS表征的测试结构
Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) Pub Date : 1900-01-01 DOI: 10.1109/ICM.2003.238501
T. Elkhatib, S. Moussa, H. Ragaie, H. Haddara
{"title":"A test structure for characterization of CMOS APS","authors":"T. Elkhatib, S. Moussa, H. Ragaie, H. Haddara","doi":"10.1109/ICM.2003.238501","DOIUrl":"https://doi.org/10.1109/ICM.2003.238501","url":null,"abstract":"A test structure to characterize CMOS APS image sensor is presented. Individual photodiodes and pixels as well as an image sensor array of 64/spl times/64 active pixels with selectable linear or logarithmic operation modes are designed. A test chip includes these features in addition to on-chip timing and control digital circuits as well as correlated double sampling have been built on a 0.6 /spl mu/m CMOS process. The test methodology and preliminary simulation results are presented.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128363475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
5 mW, 64 dB SNDR, 4/sup th/ order bandpass /spl Sigma//spl Delta/ modulator for 10.7 MHz digital IF 5 mW, 64 dB SNDR, 4/sup /阶带通/spl Sigma//spl Delta/调制器，用于10.7 MHz数字中频
Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) Pub Date : 1900-01-01 DOI: 10.1109/ICM.2003.238425
A. Noman, K. Sharaf, H. Ragai
{"title":"5 mW, 64 dB SNDR, 4/sup th/ order bandpass /spl Sigma//spl Delta/ modulator for 10.7 MHz digital IF","authors":"A. Noman, K. Sharaf, H. Ragai","doi":"10.1109/ICM.2003.238425","DOIUrl":"https://doi.org/10.1109/ICM.2003.238425","url":null,"abstract":"A 5 mW 4th order SC bandpass sigma-delta modulator is designed in 0.8-/spl mu/m CMOS process. An SNDR of 64.8 dB over 200 kHz, and image-rejection better than 80 dB are achieved by adapting double-sampling technique in circulating-delay-type resonator. The resonator is built using a high performance gain-boosted folded-cascode opamp. An improved SC-CMFB circuit is proposed to support double-sampling requirements. The opamp achieves 106 dB of DC gain, 180 MHz GBW with 750 mA at 3 V supply.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131053167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and implementation of an new Built-In Self-Test boundary scan architecture 一种新的内建自检边界扫描架构的设计与实现
Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) Pub Date : 1900-01-01 DOI: 10.1109/ICM.2003.238299
M. El-Mahlawy, E.A. El-Sehely, A. Ragab, S. Anas
{"title":"Design and implementation of an new Built-In Self-Test boundary scan architecture","authors":"M. El-Mahlawy, E.A. El-Sehely, A. Ragab, S. Anas","doi":"10.1109/ICM.2003.238299","DOIUrl":"https://doi.org/10.1109/ICM.2003.238299","url":null,"abstract":"The boundary scan (BS) technique offers a convenient alternative to physical probing. This paper presents new boundary scan architecture for Built-In Self-Test (BIST). The Boundary Scan Register (BSR) input cells have been configured to operate as a Test Pattern Generator (TPG) in the BIST mode. The BSR output cells have been configured to operate as a Multi-Input Shift Register (MISR) In the BIST mode. The Test Access Port Controller (TAPC) controls the BIST process. Instructions for BIST process are proposed. This configuration supports the BIST for both the Built-In Logic Block Observer (BILBO) register and the register transfer level. This design Implemented on the Field Programmable Gate Array (FPGA) Spartan X2C200 family.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123182771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
New expression for base transit time in an exponentially doped base bipolar transistor for all levels of injection 指数掺杂基极双极晶体管中基极输运时间的新表达式
Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) Pub Date : 1900-01-01 DOI: 10.1109/ICM.2003.237928
M. R. Rahman Khan, M. M. Shahidul Hassan, T. Rahman
{"title":"New expression for base transit time in an exponentially doped base bipolar transistor for all levels of injection","authors":"M. R. Rahman Khan, M. M. Shahidul Hassan, T. Rahman","doi":"10.1109/ICM.2003.237928","DOIUrl":"https://doi.org/10.1109/ICM.2003.237928","url":null,"abstract":"A new and compact formula for the base transit time, /spl tau//sub b/, of a modern high speed npn bipolar transistor with exponential base doping profile is derived. The present treatment includes doping dependence of mobility, bandgap narrowing effect, high injection effect and carrier velocity saturation at the base edge of the collector-base junction The derivation is not based on the charge control concept, but shows how current and charge depend on minority carrier concentration, which in turn are function of junction voltage. The expression is applicable for arbitrary injection before the onset of Kirk effect and it is simple and straight forward to give insight into device operation. The base transit time calculated analytically is compared with numerical results in order to demonstrate the validity of the assumptions made in deriving the expression.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122304987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-speed, area-efficient FPGA-based floating-point multiplier 高速、高效率的基于fpga的浮点乘法器
Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) Pub Date : 1900-01-01 DOI: 10.1109/ICM.2003.237828
G. Aty, A. Hussein, I. Ashour, M. Mones
{"title":"High-speed, area-efficient FPGA-based floating-point multiplier","authors":"G. Aty, A. Hussein, I. Ashour, M. Mones","doi":"10.1109/ICM.2003.237828","DOIUrl":"https://doi.org/10.1109/ICM.2003.237828","url":null,"abstract":"In this paper, a floating-point multiplier with high speed and area efficient is presented. The multiplier is designed, optimized, and implemented on an FPGA based system. A comparison between the results of the proposed design and a previously reported one is provided. The effect of rounding on the area, speed, and accuracy for three different configurations is examined.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115971394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
dB-linear V-I converter using composite NMOS transistor 采用复合NMOS晶体管的db -线性V-I变换器
Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) Pub Date : 1900-01-01 DOI: 10.1109/ICM.2003.238249
Quoc-Hoang Duong, Trung‐Kien Nguyen, H. Duong, Sang-Gug Lee
{"title":"dB-linear V-I converter using composite NMOS transistor","authors":"Quoc-Hoang Duong, Trung‐Kien Nguyen, H. Duong, Sang-Gug Lee","doi":"10.1109/ICM.2003.238249","DOIUrl":"https://doi.org/10.1109/ICM.2003.238249","url":null,"abstract":"A new CMOS exponential V-I converter (EVIC), based on Taylor's concept and using NMOS transistor, is presented in this paper. The proposed-modified Taylor series expansion is used to extend the dB-linear output current range. In a 0.25 /spl mu/m CMOS process, the simulations show more than 22 dB output current range and 17 dB linear range with the linearity error less than /spl plusmn/0.5 dB. The power dissipation is less than 0.3 mW with /spl plusmn/1.5 V supply voltage. The proposed EVIC can be used for the design of an extremely low-voltage and low-power variable gain amplifier (VGA) and automatic gain control (AGC).","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"11 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116780205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Hardware development and implementation of an object tracking algorithm 一个目标跟踪算法的硬件开发与实现
Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) Pub Date : 1900-01-01 DOI: 10.1109/ICM.2003.237926
I. Mahmoud, H.A. Abd El-Halym, S. Habib
{"title":"Hardware development and implementation of an object tracking algorithm","authors":"I. Mahmoud, H.A. Abd El-Halym, S. Habib","doi":"10.1109/ICM.2003.237926","DOIUrl":"https://doi.org/10.1109/ICM.2003.237926","url":null,"abstract":"This paper presents hardware development and implementation of an algorithm for object tracking. The presented parallel hardware implementation is necessary for real time tracking. The parallelism has been accomplished by implementing the computational-intensive Block Matching Algorithm (BMA) via a semisystolic array of non-programmable Processor Elements (PEs). This paper also, describes an efficient architecture for maximum repetition module for calculating the moving object centroid and its motion vector. The design is described using Synthesizable VHDL code under Xilinx foundation series 2.1, CAD environment.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131917687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low voltage low power highly linear CCIIs and its applications 低电压低功率高线性cci及其应用
Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) Pub Date : 1900-01-01 DOI: 10.1109/ICM.2003.238355
H. Hamed
{"title":"Low voltage low power highly linear CCIIs and its applications","authors":"H. Hamed","doi":"10.1109/ICM.2003.238355","DOIUrl":"https://doi.org/10.1109/ICM.2003.238355","url":null,"abstract":"In this paper, low voltage low power highly linear second-generation current conveyor (CCII) is presented. The proposed circuits are capable of operating at low voltage supply (/spl plusmn/1V), with reduced power consumption (in range of uW). PSPICE simulations results show that the -3 dB bandwidth extends beyond 138 MHz and linear voltage relation between X terminal, and Y terminal. The proposed CCIIs has many useful applications especially for low voltage low power analog filters.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114206145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
FPGA implementation of radix 2 division with over-redundant quotient selection 带过冗余商选择的基数2除法的FPGA实现
Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) Pub Date : 1900-01-01 DOI: 10.1109/ICM.2003.237827
A. A. Ibrahem, H. Elsimary, A. Salama
{"title":"FPGA implementation of radix 2 division with over-redundant quotient selection","authors":"A. A. Ibrahem, H. Elsimary, A. Salama","doi":"10.1109/ICM.2003.237827","DOIUrl":"https://doi.org/10.1109/ICM.2003.237827","url":null,"abstract":"The flexibility of field programmable gate arrays (FPGAs) can provide arithmetic intensive applications with the benefites of custom hardware but without the high cost of custom silicon implementations. In this paper present the adaptation of radix 2 division algorithm for lookup table based FPGAs implementation. This division algorithm is well suited for IEEE 754 standard operands belonging to the range. The implementation has been done with xilinx technology and FPGA-Advantage CAD tools.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"70 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124841702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new compact control unit for CNC using SoCs technology 采用soc技术的新型CNC紧凑型控制单元
Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) Pub Date : 1900-01-01 DOI: 10.1109/ICM.2003.237883
Khairy Assar, I. Ashour, E. Saad, A. Rashid
{"title":"A new compact control unit for CNC using SoCs technology","authors":"Khairy Assar, I. Ashour, E. Saad, A. Rashid","doi":"10.1109/ICM.2003.237883","DOIUrl":"https://doi.org/10.1109/ICM.2003.237883","url":null,"abstract":"This paper introduces a new complete design and implementation of a System on Chip (SoC) control unit for three dimensions CNC, using FPGA technology. Intelligent controlling software is designed and integrated in the system using a standard HPGL format. A new communication strategy for optimum utilization of the required integrated memory is introduced and implemented. The new SoC design has achieved an overall resolution of 2 micron in three-dimensional operations. The introduced SoC system replaces the microprocessors and microcontrollers based CNC control unit with highly sophisticated control circuits and also has the advantages that it can be upgraded, expanded and run at very high frequencies in comparison with microprocessor based systems.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122506617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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