5 mW, 64 dB SNDR, 4/sup /阶带通/spl Sigma//spl Delta/调制器，用于10.7 MHz数字中频

Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) Pub Date : 1900-01-01 DOI:10.1109/ICM.2003.238425

A. Noman, K. Sharaf, H. Ragai

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引用次数: 0

摘要

在0.8-/spl mu/m的CMOS工艺下，设计了一个5mw的4阶SC带通σ - δ调制器。在200 kHz范围内，采用双采样技术实现了64.8 dB的信噪比和80 dB以上的图像抑制。该谐振器采用高性能增益增强折叠级联码运放构建。提出了一种改进的SC-CMFB电路，以支持双采样要求。该opamp实现了106 dB的直流增益，180 MHz GBW, 750ma, 3v电源。

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5 mW, 64 dB SNDR, 4/sup th/ order bandpass /spl Sigma//spl Delta/ modulator for 10.7 MHz digital IF

A 5 mW 4th order SC bandpass sigma-delta modulator is designed in 0.8-/spl mu/m CMOS process. An SNDR of 64.8 dB over 200 kHz, and image-rejection better than 80 dB are achieved by adapting double-sampling technique in circulating-delay-type resonator. The resonator is built using a high performance gain-boosted folded-cascode opamp. An improved SC-CMFB circuit is proposed to support double-sampling requirements. The opamp achieves 106 dB of DC gain, 180 MHz GBW with 750 mA at 3 V supply.

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Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)

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