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2010 28th VLSI Test Symposium (VTS)最新文献

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Theoretical analysis for low-power test decompression using test-slice duplication 基于测试片重复的低功耗测试解压缩理论分析
2010 28th VLSI Test Symposium (VTS) Pub Date : 2010-05-20 DOI: 10.1109/VTS.2010.5469591
Szu-Pang Mu, M. Chao
{"title":"Theoretical analysis for low-power test decompression using test-slice duplication","authors":"Szu-Pang Mu, M. Chao","doi":"10.1109/VTS.2010.5469591","DOIUrl":"https://doi.org/10.1109/VTS.2010.5469591","url":null,"abstract":"This paper presents a single-test-input test-decompression scheme, named STSD, which utilize the technique of test-slice duplication to reduce the test-data volume as well as the signal transitions along scan paths. The encoding of STSD scheme focuses on maximizing the number of duplications made by a test-slice template. Mathematical models are also developed in this paper to estimate the compression ratio, test-application time, and scan-in transitions caused by STSD scheme, and in turn can further help designers to efficiently identify the best configuration of STSD scheme instead of going through a time-consuming simulation process. The experimental results based on large ISCAS and ITC benchmark circuits demonstrate the accuracy of the proposed mathematical models and the advantages of using STSD scheme.","PeriodicalId":176745,"journal":{"name":"2010 28th VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122514960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Scalable and accurate estimation of probabilistic behavior in sequential circuits 时序电路中概率行为的可扩展和精确估计
2010 28th VLSI Test Symposium (VTS) Pub Date : 2010-04-19 DOI: 10.1109/VTS.2010.5469586
Chien-Chih Yu, J. Hayes
{"title":"Scalable and accurate estimation of probabilistic behavior in sequential circuits","authors":"Chien-Chih Yu, J. Hayes","doi":"10.1109/VTS.2010.5469586","DOIUrl":"https://doi.org/10.1109/VTS.2010.5469586","url":null,"abstract":"We present a new methodology for fast and accurate simulation of signal probabilities in sequential logic. It can be used for analyzing soft error effects at the logic level, estimating circuit reliability, and the like. Experimental results for large benchmarks show that signal error probabilities can be estimated over many cycles with high accuracy.","PeriodicalId":176745,"journal":{"name":"2010 28th VLSI Test Symposium (VTS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114347904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Bit line coupling memory tests for single-cell fails in SRAMs 位线耦合存储器测试在sram中单个单元失败
2010 28th VLSI Test Symposium (VTS) Pub Date : 2010-04-19 DOI: 10.1109/VTS.2010.5469624
S. Irobi, Z. Al-Ars, S. Hamdioui
{"title":"Bit line coupling memory tests for single-cell fails in SRAMs","authors":"S. Irobi, Z. Al-Ars, S. Hamdioui","doi":"10.1109/VTS.2010.5469624","DOIUrl":"https://doi.org/10.1109/VTS.2010.5469624","url":null,"abstract":"Due to the decreasing dimensions of manufactured devices, the effect of bit line capacitive coupling on the behavior of faulty memory cells cannot be ignored. Neighboring cells influence the faulty behavior of defective cells through coupling. This paper analyzes and validates this behavior theoretically and through electrical simulations. The paper evaluates the impact of bit line coupling in SRAMs on cell faulty behavior and identifies necessary conditions to induce worst-case coupling effects. We present a test that guarantees detecting all single-cell static faults in the presence of capacitive coupling and worst-case neighborhood data for any possible open defect.","PeriodicalId":176745,"journal":{"name":"2010 28th VLSI Test Symposium (VTS)","volume":"26 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132737466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
On multiple bridging faults 多重桥接故障
2010 28th VLSI Test Symposium (VTS) Pub Date : 2010-04-19 DOI: 10.1109/VTS.2010.5469573
I. Pomeranz, S. Reddy
{"title":"On multiple bridging faults","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/VTS.2010.5469573","DOIUrl":"https://doi.org/10.1109/VTS.2010.5469573","url":null,"abstract":"Multiple faults are typically detected by test sets for single faults. For bridging faults, we show that fault activation conditions are more difficult to create for certain multiple faults than for the single faults that comprise them. As a result, a test set for single bridging faults may leave significant percentages of detectable multiple faults undetected. We discuss three such cases, corresponding to three types of bridging faults, and present experimental results for one of them. As part of this study we consider the ability of a 10-detection test set for single stuck-at faults to detect multiple bridging faults of this type.","PeriodicalId":176745,"journal":{"name":"2010 28th VLSI Test Symposium (VTS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123229245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
At-speed scan test with low switching activity 低开关活动的高速扫描试验
2010 28th VLSI Test Symposium (VTS) Pub Date : 2010-04-19 DOI: 10.1109/VTS.2010.5469580
Elham K. Moghaddam, J. Rajski, S. Reddy, M. Kassab
{"title":"At-speed scan test with low switching activity","authors":"Elham K. Moghaddam, J. Rajski, S. Reddy, M. Kassab","doi":"10.1109/VTS.2010.5469580","DOIUrl":"https://doi.org/10.1109/VTS.2010.5469580","url":null,"abstract":"This paper presents a novel method to generate test vectors that mimic functional operation from switching activity point of view. The method uses states obtained by applying a number of functional clock cycles starting from the scan-in state of a test vector to fill the unspecified scan cell values in test cubes. Experimental results presented for industrial circuits demonstrate the effectiveness of the proposed method.","PeriodicalId":176745,"journal":{"name":"2010 28th VLSI Test Symposium (VTS)","volume":"52 3S3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124518527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 94
A novel hybrid delay testing scheme with low test power, volume, and time 一种新型的低功耗、低体积、低时间的混合延迟测试方案
2010 28th VLSI Test Symposium (VTS) Pub Date : 2010-04-19 DOI: 10.1109/VTS.2010.5469547
Zhen Chen, S. Seth, D. Xiang
{"title":"A novel hybrid delay testing scheme with low test power, volume, and time","authors":"Zhen Chen, S. Seth, D. Xiang","doi":"10.1109/VTS.2010.5469547","DOIUrl":"https://doi.org/10.1109/VTS.2010.5469547","url":null,"abstract":"Test power, volume, and time are the major test cost parameters that must be minimized while achieving the desired level of fault coverage. Unlike prior research in delay fault testing that has focused on at most two test cost parameters, the hybrid (LOS+LOC) scheme proposed here simultaneously considers all three cost parameters and achieves better fault coverage than prior schemes, as demonstrated by experimental results. A factor of (n/logn) reduction in test power is achieved by the use of a nonlinear double-tree-scan (DTS) structure instead of linear scan chain of length n. Concomitantly, by exploiting the permutation feature of DTS, whereby the same test data can be loaded in multiple ways, we also achieve substantial reductions in the test-data volume. By incorporating the Illinois scan (ILS) within this framework, we minimize not only the test time but also achieve further reductions in test-data volume.","PeriodicalId":176745,"journal":{"name":"2010 28th VLSI Test Symposium (VTS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127032762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Defect diagnosis based on DFM guidelines 基于DFM指南的缺陷诊断
2010 28th VLSI Test Symposium (VTS) Pub Date : 2010-04-19 DOI: 10.1109/VTS.2010.5469577
Dongok Kim, I. Pomeranz, M. E. Amyeen, S. Venkataraman
{"title":"Defect diagnosis based on DFM guidelines","authors":"Dongok Kim, I. Pomeranz, M. E. Amyeen, S. Venkataraman","doi":"10.1109/VTS.2010.5469577","DOIUrl":"https://doi.org/10.1109/VTS.2010.5469577","url":null,"abstract":"Following design-for-manufacturability (DFM) guidelines during chip design can lower the possibility of occurrence of systematic defects. In this paper, we investigate the use of DFM guidelines during the defect diagnosis process with the goal of identifying which DFM guidelines are responsible for the defects present in failing chips. We also introduce a new metric called diagnostic coefficient that allows us to rank the guidelines according to their contribution of hard-to-diagnose defects. DFM guidelines that are ranked high should be applied during chip design in order to obtain chips that are easier to diagnose.","PeriodicalId":176745,"journal":{"name":"2010 28th VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126957086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST 可靠的缓存设计与片上监测NBTI退化的SRAM细胞使用BIST
2010 28th VLSI Test Symposium (VTS) Pub Date : 2010-04-19 DOI: 10.1109/VTS.2010.5469614
Fahad Ahmed, L. Milor
{"title":"Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST","authors":"Fahad Ahmed, L. Milor","doi":"10.1109/VTS.2010.5469614","DOIUrl":"https://doi.org/10.1109/VTS.2010.5469614","url":null,"abstract":"Constant scaling in device dimensions and increasing operating temperatures and vertical electrical fields have all contributed to faster device aging due to NBTI. The problem is further compounded in SRAM cells where the devices are among the smallest for a technology node. Since NBTI degradation is a gradual process, it is proposed that if the threshold voltage increase in PMOS devices of SRAM cells can be monitored, cache arrays with failing cells can be reliably operated after reconfiguration, given available memory redundancy. Using an experimentally verified NBTI model, we study DC noise margins in conventional 6T SRAM cells, as a function of NBTI degradation, in the presence of process variations. An on-chip NBTI monitoring scheme is presented that can be embedded within conventional cache designs without affecting normal device operation, enabling the prediction of cell failure before its occurrence.","PeriodicalId":176745,"journal":{"name":"2010 28th VLSI Test Symposium (VTS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127621452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
An ADC/DAC loopback testing methodology by DAC output offsetting and scaling 通过DAC输出偏移和缩放的ADC/DAC环回测试方法
2010 28th VLSI Test Symposium (VTS) Pub Date : 2010-04-19 DOI: 10.1109/VTS.2010.5469548
Xuan-Lun Huang, Jiun-Lang Huang
{"title":"An ADC/DAC loopback testing methodology by DAC output offsetting and scaling","authors":"Xuan-Lun Huang, Jiun-Lang Huang","doi":"10.1109/VTS.2010.5469548","DOIUrl":"https://doi.org/10.1109/VTS.2010.5469548","url":null,"abstract":"This paper presents a loopback methodology for static linearity testing of an ADC/DAC pair; the key idea is to raise the effective ADC and DAC resolution by scaling the DAC output. First, during ADC testing, we scale down the DAC output to achieve the needed test stimulus resolution and adjust the DAC output offset to cover the ADC full-scale range. Then, for DAC testing, we raise the effective ADC resolution by scaling up the DAC output. Both simulation and measurement results are presented to validate the proposed technique.","PeriodicalId":176745,"journal":{"name":"2010 28th VLSI Test Symposium (VTS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131676459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Low-power test planning for arbitrary at-speed delay-test clock schemes 任意高速延迟测试时钟方案的低功耗测试规划
2010 28th VLSI Test Symposium (VTS) Pub Date : 2010-04-19 DOI: 10.1109/VTS.2010.5469607
Christian G. Zoellin, H. Wunderlich
{"title":"Low-power test planning for arbitrary at-speed delay-test clock schemes","authors":"Christian G. Zoellin, H. Wunderlich","doi":"10.1109/VTS.2010.5469607","DOIUrl":"https://doi.org/10.1109/VTS.2010.5469607","url":null,"abstract":"High delay-fault coverage requires rather sophisticated clocking schemes in test mode, which usually combine launch-on-shift and launch-on-capture strategies. These complex clocking schemes make low power test planning more difficult as initialization, justification and propagation require multiple clock cycles. This paper describes a unified method to map the sequential test planning problem to a combinational circuit representation. The combinational representation is subject to known algorithms for efficient low power built-in self-test planning. Experimental results for a set of industrial circuits show that even rather complex test clocking schemes lead to an efficient low power test plan.","PeriodicalId":176745,"journal":{"name":"2010 28th VLSI Test Symposium (VTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126595482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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