Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST

Abstract

Constant scaling in device dimensions and increasing operating temperatures and vertical electrical fields have all contributed to faster device aging due to NBTI. The problem is further compounded in SRAM cells where the devices are among the smallest for a technology node. Since NBTI degradation is a gradual process, it is proposed that if the threshold voltage increase in PMOS devices of SRAM cells can be monitored, cache arrays with failing cells can be reliably operated after reconfiguration, given available memory redundancy. Using an experimentally verified NBTI model, we study DC noise margins in conventional 6T SRAM cells, as a function of NBTI degradation, in the presence of process variations. An on-chip NBTI monitoring scheme is presented that can be embedded within conventional cache designs without affecting normal device operation, enabling the prediction of cell failure before its occurrence.